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We experimentally demonstrate automatic optical linearization of a Ring Assisted MZ modulator with SFDR > 110dB.Hz2/3, fabricated in a silicon photonic foundry process. The linearization algorithm reconfigures the modulator to its optimum SFDR or other desired regimes regardless of random phase offsets and process/temperature variations.

Hybrid integration of the resistive Random Access Memory (RRAM) arrays with standard CMOS has gained recent attention for realization of neuromorphic computing hardware. Such architectures are expected to result in orders of magnitude higher energy-efficiency than their digital counterparts. While a few fully-connected neural networks have been realized using RRAM arrays, a parallel hardware implementation of convolutional neural networks (CNNs) has lagged due to the sequential nature of processing. Prominent reasons include high device variability, lower yield of fabricated 1T1R RRAM devices, and the challenges associated with the retention of multi-levels states in RRAM synapses due to their resistance drift. In this work, we propose and analyze a hybrid solution where constant-g m CMOS-RRAM cells hold the kernel weights and CMOS mirrors are used for Spiking Neural Network (SNN) processing. This is in contrast with the approaches where all weights are implemented using individual 1T1R cells, or addressing is used to route spikes to an SNN that only implements the CNN kernel.

Emerging nonvolatile memory (NVM) devices are being intensely researched to realize energy-sustainable hardware for Edge-Artificial Intelligence applications. Mixed-Signal neuromorphic computing paradigm aims to leverage these NVMs to perform artificial neural network (ANN) computations inside high-density memory arrays in analog domain resulting in significant energy efficiency gain over digital realizations. While the challenges of variability, resolution, retention, and endurance of RRAM devices are being addressed, only meagre attention has been paid to the active neuron circuits that drive the memory arrays. While a CMOS neuron needs to drive a large fan-out of resistive devices with very low quiescent current, CMOS process variability can affect the overall neural network performance. In this work, the effects of process-induced variations are analyzed for RRAM-compatible CMOS neurons and a novel design is presented to mitigate these effects and allow low-power inference.

Recent developments in silicon photonic (SiP) integrated circuits have opened new avenues for analog circuit designers to explore hybrid integration of photonic with standard CMOS electronics. SiP platforms provide the opportunity to realize these systems in a compact chip-scale form factor and alleviate long-standing challenges with the optical devices. In this work, we analyze analog RF photonic link using Ring-Assisted Mach Zehnder Modulator (RAMZM) for high linearity. We analyze the gain, noise figure, and linearity metrics associated with the RAMZM based link and present design trade-offs.

A gamut of emerging non-volatile memory (NVM) devices, aka memristors, are currently being explored for mixed-signal hardware implementation of artificial neural networks. These constitute vector by matrix multipliers (VMMs) and Neuromorphic computing circuit implementations using NVM crossbar arrays. However, transistor-level circuit designers need to accommodate non-ideal behavior of these devices, that includes variability, low-resistance, finite resolution, relaxation of states, and endurance. In this work, we explore techniques for two-terminal high-LRS (low resistance state) synapses/weights using CMOS-NVM integration that are essential for energy-efficient implementation of Neuromorphic System-on-a-Chip (NeuSoC).

A scheme to realize Optical PAM-4 transmitter by driving a three-segment microring modulator with tunable voltage-mode drivers is presented. This proposed scheme provides linearly spaced PAM-4 levels and is further categorized into two schemes, namely higher "0" and lower "1" tuning. The two schemes are verified using co-simulation of voltage-mode drivers implemented in 65nm CMOS and Verilog-A compact models for photonic components based on a silicon photonic process from IMEC. Also, the robustness of our proposed scheme can be proved by achieving high linearity when phase-shifter length variation is present.

Silicon photonic interconnects have the potential to break bandwidth-distance limitations intrinsically associated with electrical links. This paper presents a dual-mode NRZ/PAM4 silicon photonic transmitter based on a segmented-electrode Mach-Zehnder Modulator (SE-MZM). The electrical portion of the transmitter, fabricated in a 16nm FinFET process, utilizes stacked-CMOS push-pull driver stages that include a parallel asymmetric fast discharging path to compensate for the slow transition edge caused by the nonlinear capacitance of the reversed-biased MZM diode segments. High-speed PAM4 modulation is achieved with phase interpolators for coarse delay control between the MSB and LSB segments and by employing independent digital-controlled delay lines on a per-segment basis to match the optical propagation delay. The 56 Gb/s optical transmitter achieves 9.5 dB extinction ratio and 12.6 pJ/bit power efficiency, excluding laser power, when driving the flip-chip bonded MZM designed in a 130 nm SOI process.

In this article, a Ring-Assisted-Mach-Zehnder-Interferometer (RAMZI) based RF-to-Optical Modulator with excellent spurious-free-dynamic-range (SFDR) performance has been presented. The performance of this silicon-based RAMZI device has been analyzed and verified with a commercial Photonic Circuit simulation tool. A compact Verilog-A model of RAMZI is also developed for hybrid CMOS circuit in Cadence environment. An SFDR of $129.97 \mathrm {d}\mathrm {B}/\mathrm {H}\mathrm {z}^{2/3}$ has been obtained for this type of modulator.

A compact time-domain Verilog-A modeling methodology is developed for PIC simulation in Cadence environment. With this methodology, basic building blocks for optical system are derived to form the model of coupling-based ring modulator. Parameters used in the developed models are extracted from IMEC PDK. One design example of the coupling-based ring modulator is discussed and both of its transmission and transient results are presented. The final Cadence simulation results show that the proposed coupling-based ring modulator can realize tunable coupling-coefficient and renders larger extinction ratio than regular ring modulator.

Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface need immediate attention from the community. In this work, we perform energy-estimation of a NeuSoC system and predict the desirable circuit and device parameters for energy-efficiency optimization. Also, CMOS synapse circuits based on the concept of CMOS memristor emulator are presented as a system prototyping methodology, while practical memristor devices are being developed and integrated with general-purpose CMOS. The proposed mixed-signal memristive synapse can be designed and fabricated using standard CMOS technologies and open doors to interesting applications in cognitive computing circuits., Comment: This is a preprint of proceedings in IEEE International Symposium on Circuits and Systems (ISCAS), May 2018. Copyright 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See \URL{http://www.ieee.org/publications\_standards/publications/rights/index.html} for more information

Compact behavioral models for silicon photonic Mach-Zehnder modulators (MZM) are developed for SPICE compatible electro-optical co-simulation. The model captures electro-optical interactions and dynamics, optical insertion loss and thermo-optical effect. Behavioral model simulation results and measurement results are shown to be a highly match. The model will be an indispensable part of the optical process design kit (PDK) which can be provided to the integrated circuit designers for hybrid simulation.

Low-cost optical interconnects are playing an important role in sustaining the exponential growth in data center demand and to support the future internet-of-things cloud infrastructure. These chip-scale optical transceiver systems are integrated using two-chip bonding solution of CMOS electronic die with a silicon photonic die. In this work, modeling of the critical bond-wire is performed with electromagnetic field solver to optimize the integration of a silicon photonic transmitter, which is composed of a current mode driver in a 130 nm CMOS process and a traveling-wave Mach-Zehnder modulator (MZM) in a SOI photonic process, respectively. It is shown that the bond-wire can be optimized for bandwidth extension using series peaking with the open-drain current mode driver. However, it degrades the bandwidth when using a voltage mode driver. A compact, experimentally verified, Verilog-A model for the MZM is adopted for the electro-optical simulation. Further, it is demonstrated that a minimum length of the bond-wire and a minimum spacing between two signal bond-wires are required to ensure the bandwidth of the system with hybrid simulation. A MZM device chip-on-board wire bonded on PCB is demonstrated operating up to 12.5 Gb/s.

Pipelined and Delta-Sigma (ΔΣ) ADCs are increasingly becoming popular in mixed-signal system-on-chip (SoCs). This tutorial combines theoretical as well as practical perspectives on ADC design with special focus on two types of ADCs, viz., CT-ΔΣ ADC and pipelined ADC. The goal is to provide a complete picture to the audience, starting from system level architecture to their transistor-level design. The tutorial will cover basics of ΔΣ modulation, both continuous-time (CT) as well as discrete-time, and pipelined ADCs. System-level behavioral modeling using Matlab/Simulink environment will be presented. The top-down design approach will discuss circuit implementation and include circuit non-idealities in the behavioral modeling. Case studies will be presented for CT ΔΣ ADCs and various digital calibration techniques for pipelined ADCs.

Magnetrons are efficient and robust, but phase-controlled magnetrons are difficult to implement. Our prior work [1] has used 2D simulations of a rising sun magnetron to demonstrate that the magnetron phase can be controlled by modulating the electron injection at discrete locations to control formation of the electron spokes. These results have further shown that such phase control can be achieved if only 10% of the injected current is modulated. We are currently designing a magnetron experiment that will use the 10-cavity circuit of a commercially available cooker magnetron from L3 Communications. Although the CWM-75KW magnetron can operate at high power (75 kW), our experiment will utilize the devices ability to operate at lower power and voltage (

An accurate methodology for analyzing the Mach-Zehnder modulator (MZM) based optical link power budget is presented. It optimizes the transceiver's system-level performance to meet the specifications of the optical links with N-level (N=2,4,8) pulse amplitude modulation format for high-speed signaling.

A 4-level pulse amplitude modulation (PAM-4) silicon photonic transmitter targeting operation at 25 Gb/s is designed using an electrical-photonic co-design methodology. The prototype consists of an electrical circuit and a photonics circuit, which were designed in 130 nm IBM SiGe BiCMOS process and 130nm IME SOI CMOS process, respectively. Then the two parts will be interfaced via side-by-side wire bonding. The electrical die mainly includes a 12.5 GHz PLL, a full-rate 4-channel uncorrelated 27 − 1 pseudo-random binary sequence (PRBS) generator and CML drivers. The photonics die is a 2-segment Mach-Zehnder modulator (MZM) silicon photonics device with thermal tuning feature for PAM-4. Verilog-A model for the MZM entails the system simulation for optical devices together with electrical circuitry using custom IC design tools. A full-rate 4-channel uncorrelated PRBS design using transition matrix method is detailed, in which any two of the 4-channels can be used for providing random binary sequence to drive the two segments of the MZM to generate the PAM-4 signal.

A compact Verilog-A model of silicon-based junction traveling-wave Mach-Zehnder modulator (MZM) is developed for hybrid CMOS and photonic system-level simulation in Cadence environment. Critical device functions such as the voltage depen- dent change of refractive index, small-signal RLGC parameters for the MZM arms are extracted from the photonic device characterization from OpSIS foundry. Thermo-optical coefficient is also considered in the model. Simulation results including electro-optic S21 is characterized for the phase modulator's bandwidth. Also, transient MZM operation with non-return to zero (NRZ) data transmission at 10 Gb/s and 20 Gb/s rates are demonstrated. Index Terms—CMOS Photonics, Compact model, MZM, NRZ, Verilog-A.

Continuous-time delta sigma (CT-ΔΣ ) ADCs are gaining wider adoption in data conversion systems primarily aided by their robustness to mismatch in nano-scale CMOS technologies and inherent anti-alias filtering. In past, several techniques have been employed to achieve wider conversion bandwidths by either scaling the designs to a lower technology node or by adopting architectures with lower oversampling ratios (OSR). Cascaded, or MASH, CT-ΔΣ ADCs have been explored to achieve conversion bandwidths by cascading lower order ΔΣ loops followed by a digital coarse quantization noise canceling filter (NCF). Another technique which has recently been explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle (Ts) in the loop. However, these techniques individually cannot sufficiently meet the ever increasing bandwidth demand for the broadband wireless applications. Further, the ELD > Ts designs require an extra modulator order to achieve the same noise-shaping performance as the low-speed ELD

A 10-Gb/s integrated limiting receiver for silicon photonics interconnects is proposed with detailed system level and circuit level design and analysis. Silicon photonics devices fabricated in silicon-on-insulator (SOI) can be seamlessly integrated with standard CMOS process, which allows compact system integration and significantly lower power dissipation. By taking the advantages of low parasitic capacitance of the on-chip Germanium (Ge) detector and adopting bandwidth extension techniques, a total bandwidth of 7.2 GHz with 87 mW power consumption is obtained in a 0.13-μm CMOS process. The final differential output signal has a peak-to-peak swing of about 1.2 V and a peak-to-peak jitter of 14.3 ps and 9.8 ps for 10-Gb/s 27 - 1 PRBS data with an average received optical power of -17 dBm and 0 dBm, respectively.

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.

A 1 GS/s Continuous-time Delta-Sigma modulator (CT-ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB signal-to-noise is reported in a 0.13µm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT-ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT-ΔΣM has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.

Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-ΔΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-ΔΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.

The design considerations for low-power continuous time (CT) delta-sigma (ΔΣ) modulators is studied and circuit design details for a 13.5 bit modulator are given. The converter has been designed in a 0.5 um C5FN AMI CMOS technology and achieves a maximum signal-to-noise ratio (SNR) of 85 dB in a 48 kHz bandwidth and dissipates 5.4 mW from a 5 V supply when clocked at 6.144 MHz. It features a third-order active-RC loop filter, a 4-bit flash quantizer along with a Data Weighted averaging (DWA). The loop filter architecture and its coefficients have been targeted for the minimum power dissipation. The DWA also has been implemented by standard cell based synthesis to further optimize power. The figure of merit (FoM) of the CT-ΔΣ modulator is 3.71 pJ/bit. The fabricated chip of the modulator occupies an area of 4.5 mm2.

A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ΔΣ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ΔΣ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12mm2 and consumes 8 mW power from the 1.1V supply.

A 500 MS/s, wideband 4th order continuous-time delta sigma modulator (CT-ΣΔM) using a two-step 5-bit quantizer, consisting of only 10 comparators, is proposed and presented using 0.18µm CMOS technology. A proposed modulator takes advantage of the high resolution two step quantization technique and an excess loop compensation of more than one cycle to achieve a low-power, high dynamic range with a wide conversion bandwidth. A robust systematic design method is used to determine the loop filter coefficients by considering the non-ideal opamps effects including the finite gain and the presence of multiple internal poles and zeros. The proposed CT-ΣΔM achieves a dynamic range of 75.83 dB, peak SNR of 75.1 dB with 25 MHz bandwidth (OSR = 10) while consuming only 27.5 mW from the 1.8 V supply. The relevant design trade offs have been investigated and presented with simulation results.

Over the past decade CMOS technology has been continuously scaling which has resulted in sustained improvement in transistor speeds. However, the transistor threshold voltages do not decrease at the same rate as the supply voltage (V DD ). Besides, the open-loop gain available from the transistors is diminishing. This trend renders the traditional techniques, like cascoding and gain boosting, less useful for achieving high DC gain in nano-scale CMOS processes. Thus, horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low-V DD processes. This paper presents a design procedure for op-amp design using split-length compensation. A reversed-nested split-length compensated (RSLC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RSLC topology is then extended to the design of three-stage fully-differential op-amps.

A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fully-differential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 µm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes the K-Delta-1- Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared opamp and K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area.

This paper presents the design and experimental results of W-2W current mirror binary-weighted current steering digital-to-analog converter (DAC) and its application for programming phase change memory (PCM). This new approach significantly reduces the layout area of current-mode DACs by the virtue of its compact size. The proposed DAC can replace the write driver circuits in phase change memories. Both 6-bit and 12-bit DACs have been fabricated in 0.5 mum CMOS technology. The layout size of the 12-bit and the 6-bit DACs is 0.09 mm 2 and 0.04 mm 2 respectively. Experimental results are presented and the limitations are discussed.

Theoretical and experimental results are presented for op-amp compensation using split-length transistors. By using split-length devices the right-half plane zero which plagues op-amp performance can be eliminated. Experimental results indicate substantial enhancements in speed while reducing power consumption and layout area. Further, these techniques can be used to compensate op-amps when using small supply voltage (VDD).

This paper illustrates design, fabrication and testing of novel differential high-speed digital input buffers. The delay of the proposed input buffers are nearly independent of power supply voltage and input signal amplitudes. The pulse shape of the output signal is highly symmetric which mitigates skew related errors.

This paper presents the design of CMOS op-amps using indirect feedback compensation technique. The indirect feedback compensation results in much faster and low power op-amps, significant reduction in the layout size and better power supply noise rejection.

This paper details the design of a MEMS sensor to detect swelling of polymer films. The sensor is a variable capacitor composed of two electrodes separated by a chemically sensitive polymer. The polymer is chosen such that it absorbs target chemicals (analytes). Upon analyte absorption, the polymer swells, which increases the distance between the two electrodes. This changes the capacitance of the device and can be electrically detected and measured. This paper presents the design of the sensor, the fabrication steps, and polymer selection criteria for the sensor.

This paper describes the development of a MEMS sensor system to detect volatile compounds. The sensor consists of a MEMS capacitive sensor element monolithically integrated with a sensing circuit. The sensor element is a parallel plate capacitor using a chemically sensitive polymer as the dielectric. In presence of the target analyte, the polymer swells and changes the capacitance of the sensor element. This change in capacitance is sensed and converted to a digital bit stream by a delta-sigma sensing circuit. This paper provides an overview of the design of the sensor element, the sensing circuit and the process integration for their fabrication on a single die.

The understanding of tumor oxygenation at the microvascular level in an orthotopic model may provide useful insight into tumor physiology, therapeutic response and development of protocols to study tumor behavior. In this paper the vascular status and the patho-physiological changes occurring during angiogenes is are studied in an orthotopic brain tumor model using a noninvasive multimodality approach based on near infrared (NIR) diffuse optical spectroscopy (DOS) along with magnetic resonance imaging (MRI) We report a direct correlation between tumor size and intratumoral microvessel density MVD, and tumor oxygenation. The relative decrease in the oxygen saturation value with tumor growth indicates that though blood vessels infiltrate and proliferate the tumor region, a hypoxic trend is clearly present