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In this paper, we investigate the behavior of 1200V Punch-Through, Trench gate, Field stop (FS) IGBT at various temperatures for different trench widths and depths. MOS-controlled devices with trench gates are the most desirable as their reduced VCE(sat) enables increased conduction current density in high power applications. The paper describes the simulation results of the trench gate IGBT. The effect caused in the I-V characteristics of IGBT by the trench design has been investigated for the first time. The results have been compared with different trench sizes. Technology-computer-aided-design (TCAD) simulations with Sentaurus and analytical solution reveal that the breakdown occurs under the gate. By enlarging the gate length, more freedom for conductivity modulation is provided decreasing the conduction losses. Trench gates provide higher channel density (small cell size) and reduce the JFET resistance in the IGBT structure. It is observed that the variation in trench width and depth affects the breakdown voltage, VCE(sat) and switching characteristics in turn varying the stability of the device. This device design not only reduces the chip size, but also improves current handling capability and latch-up current density.

This paper presents a low cost innovative dual channel engineering to simulate the effects of arsenic and antimony implantation over breakdown voltage and on state resistance of an Ultra High Voltage (UHV) device. There are many devices in market with multiple conduction paths, but all these devices use high energy implants. But we have used a low cost and low energy implant over P-top to form an extra conduction path. Optimizations are done to obtain high breakdown voltage and lower Ron by varying the P-top and Ntop over P-top. We demonstrate interface charge analysis for both Antimony and Arsenic implantation over P-top and also we investigate the effect of N-top implantation before and after NDrift diffusion on breakdown voltage.