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Spin-transfer torque magnetoresistive random access memory (STT-MRAM) is among the most promising candidates for emerging memories. Thus, reliable simulation tools are mandatory to provide an important aid for understanding and improving the design of such devices. In this work we are concerned with the simulation of STT-MRAM. The well-known Landau-Lifshitz-Gilbert (LLG) equation describes the magnetization dynamics. Since we are dealing with STT-MRAM, an additional torque term must be added to the LLG equation. The torque acting on the magnetization is generated by the nonequilibrium spin accumulation due to the electric current flowing through the structure. The partial differential LLG equation with the additional torque computed from the spin accumulation is solved using the highly efficient finite element method (FEM). We implemented several time integration schemes using an open-source FEM library. In order to verify and calibrate the FEM implementation, we compared it to a finite difference method (FDM) implementation used as a reference. By properly tailoring the time integration scheme and the time step size, almost identical simulation results as with the FDM are achieved. Proper calibration is essential in order to simulate a more realistic multi-layer structure with a composite switching layer consisting of ferromagnetic layers separated by nonmagnetic buffers.

We present the use of reinforcement learning for the discovery of pulse sequences for optimal switching of spin-orbit torque magnetoresistive memory devices. A neural network trained on fixed material parameters is able to switch a memory cell for a wide range of material parameter variations as well as for sub-critical current values. Micromagnetic simulations are used to prove the reliability of the trained neural network.

As the interest in spin-transfer torque magnetoresistive memories for embedded and stand-alone applications is growing, reliable simulation tools are needed to help design and improve these devices. In this paper, we present a finite element implementation of the drift-diffusion approach for coupled spin and charge transport, commonly applied in metallic valves, to compute the torques acting in a magnetic tunnel junction which constitutes the cell of modern spin-transfer torque memories. We investigate the dependence of the torques on system parameters and demonstrate that it is possible to employ the drift-diffusion approach to reproduce the torque magnitude expected in magnetic tunnel junctions. We further show that a full 3D solution of the equations is necessary in order to accurately model the torques acting on the magnetization. The use of a unique set of equations for the whole memory cell constitutes the basis of an efficient finite element based approach to rigorously describe the switching process of novel spin-transfer torque memories.

Employing novel 2D materials with topologically protected current-carrying edge states is promising to boost the on-current in electronic devices. Using nanoribbons is essential to reduce the contribution of the 2D bulk states to the current. Making the nanoribbon widths narrower allows one to put more current-carrying edge states under the gate of a fixed width thus boosting the current. However, the edge states start to interact in narrow nanoribbons. Based on an effective k·p model, we analyze the topologically protected edge states and their conductance for several 2D materials as a function of the normal electric field. We compare the 2D materials MoS 2 , MoSe 2 , WS 2 , and WSe 2 in the topological 1T′ phase and find the largest electric field-induced conductance modulation is in MoS 2 nanoribbons.

Exploiting novel materials with advanced properties is necessary to improve device performance and continue with their scaling for high performance applications at reduced power. Among these materials, topological insulators (TIs) present an exciting opportunity where the highly conductive edge states, which are protected against back scattering, can lead to advances in electronic as well as spin controlled devices. Here, we present first principles results that evaluate topologically protected edge states in MoS 2 nanoribbons. We vary the width of the nanoribbons and show that they transition to trivial insulators below a critical width. Furthermore, the trivial insulator can be a direct or indirect band gap insulator depending on the width and the edge termination. Our results show that including realistic edge terminations can provide valuable insight, especially for narrow width TIs.

Micromagnetic simulations of MRAM cells are a computationally demanding task. Different methods exist to handle the computational complexity of the demagnetizing field, the most expensive magnetic field contribution. In this work we show how the demagnetizing field can efficiently be calculated in complex memory structures and how this procedure can be further used to simulate spin-transfer torque switching in magnetic tunnel junctions.

Surface Green’s functions describe the coupling of the device region with the attached leads. A lead represents a semi-infinite region with uniform properties such as cross section and electrostatic potential. The scattering states in the leads can be determined in different ways. In this work we exploit the uniformity of the system and formulate the problem in reciprocal space where the Green’s function takes on a simple form. A Fourier transformation yields the elements of the Green’s function in real space. We present the principal steps of this calculation and discuss results for nanoribbons. The 2D materials considered are graphene and $\mathrm{M}\mathrm{o}\mathrm{S}_{2}$ in the 1T’ phase, their electronic structure is represented by k$\cdot$ p Hamiltonians.

Spin-transfer torque based devices are among the most promising candidates for emerging nonvolatile memory. Reliable simulation tools can help understand and improve the design of such devices. In this paper, we extend the drift-diffusion approach for coupled spin and charge transport, commonly applied to determine the torque in metallic valves, to the case of magnetic tunnel junctions, which constitute the cell of modern spin-transfer torque memories. We demonstrate that, by introducing a magnetization dependent conductivity and properly choosing the spin diffusion coefficient in the tunnel barrier, the expected behavior of both, the electric current and the spin accumulation, is properly reproduced. The spin torque values’ dependence on the system parameters is investigated. As a unique set of equations is used for the entire memory cell, this constitutes the basis of an efficient finite element based approach to rigorously describe the magnetization dynamics in emerging spin-transfer torque memories.

Continuous miniaturization brought the feature size of silicon technology into the nanometer scale, where performance enhancement cannot be easily achieved by further feature size reduction. The use of new materials with advanced properties has become mandatory to meet the needs for higher performance at reduced power. Topological insulators possess highly conductive topologically protected edge states insensitive to scattering and thus suitable for energy efficient high speed devices. Here, we evaluate the subband structure in a nanoribbon of 1T’-MoS2 by applying an effective k·p Hamiltonian in a confined geometry.

We demonstrate the switching of a perpendicularly magnetized free layer by spin-orbit torques. The switching is accomplished by a purely electrical, two-current pulse scheme. The first pulse realizes the selection of the cell, while the second pulse, with a lower current, completes the switching deterministically. The second current is reduced by 50% without affecting the switching performance. This current reduction results in a reduction of about 80% of the power consumption by the second pulse. Even with such a large decrease of current and power, the switching time remains robust and fast, resulting in a very efficient switching scheme.

A drift-diffusion approach to coupled spin and charge transport has been commonly applied to determine the spin-transfer torque acting on the magnetization in metallic valves. This approach, however, is not suitable to describe the predominant tunnel transport in magnetic tunnel junctions. Here we demonstrate that by introducing a magnetization dependent resistivity and adjusting the spin diffusion coefficient one can successfully apply the generalized spin and charge drift-diffusion approach also to magnetic tunnel junctions. As a unique set of equations is used for the entire structure, this paves the way to develop an efficient finite element based approach to describe the magnetization dynamics in emerging spin-transfer torque memories.

We evaluate the subband structure in a narrow nanoribbon of 1T’ molybdenum disulfide by employing an effective $\mathrm{k}\cdot \mathrm{p}$ Hamiltonian. Highly conductive topologically protected edge states whose energies lie within the bulk band gap are investigated. Due to the interaction of the edge modes located at the opposite edges, a small gap in their linear spectrum opens in a narrow nanoribbon. This gap is shown to sharply increase with the perpendicular out-of-plane electric field, in contrast to the behavior in a wide nanoribbon. The gaps between the electron and hole bulk subbands also increase with the electric field. The increase of the gaps between the subbands leads to a rapid decrease of the ballistic nanoribbon conductance and current with the gate voltage, which can be used for designing molybdenum disulfide nanoribbon-based current switches.

The magnetization dynamics of a free layer in spin-transfer torque MRAM is usually determined by the torque created by a position-independent current density. In circuits, the voltage, not current density, is fixed during switching. Therefore, the approximate evaluation of the torque based on the fixed current density becomes questionable in modern magnetic tunnel junctions with a tunneling magnetoresistance ratio of about 200%, where the current densities across the structure can vary by a factor of three. We compare the switching times obtained within a fixed voltage assumption with those from the approximate fixed current density approach. We demonstrate that the fixed current approach can reproduce the correct switching also in the case of high TMR, if the current is appropriately adjusted. It is shown that the correction to the current is not universal and depends on the temperature and the switching speed.

As scaling of electronic semiconductor devices - the main driving force behind an outstanding increase of computing power of modern electronic circuits - displays signs of saturation, the main focus of engineering research in microelectronics shifts towards finding new computing paradigms. The future solutions must be scalable and energy efficient while delivering high computational performance, superior to that of CMOS-based circuits. In order to benefit from the outstanding potential of highly advanced silicon processing technology, the emerging solutions must be CMOS compatible. Emerging nonvolatile memories, including magnetoresistive memories, satisfy the necessary requirements: Purely electrically addressable magnetoresistive random access memories yield all aforementioned conditions. They possess a simple structure, require fewer extra masks for fabrication, and offer endurance and speed superior to those of flash memory. Fast operation of magnetoresistive memories makes them a viable contender to static random access memory and flash memory for embedded applications in Systems on Chip. Having nonvolatile memory very close to CMOS removes the necessity of the energy-intensive data transfer from the main memory to the CPU and offers a prospect of data processing in the nonvolatile segment, where the same elements are used to store and to process the information. This opens perspectives for conceptually new low power and highperformance computing paradigms based on logic-in-memory and in-memory computing.

Simulations of free-layer switching in spin - transfer torque MRAM are usually performed with the torque computed approximately by assuming a position-independent electric current density through the structure. For high values of the tunneling magnetoresistance, this description is not accurate anymore, and one needs to solve the spin and charge drift-diffusion equations in the whole structure self-consistently. We compute the switching time distribution obtained by the self-consistent model and compare it to the switching times from the fixed current density approach. We show that, provided the current is appropriately adjusted, the simplified model can mimic the correct switching time distribution even in the case of high TMR.

We investigate the switching of a symmetric square and an elongated rectangular perpendicular free layer by spin-orbit torque with a magnetic field-free two-pulse scheme. The switching of the layer is achieved by utilizing the in-plane shape anisotropic magnetic field. For making the switching of a symmetric square layer deterministic, an in-plane stray field created in a part of the layer is used. The combination of the shape and stray fields accelerates the switching of the free layer significantly. A switching speedup factor of 3 to 5 has been obtained. The strategy also improves the robustness of the scheme allowing fast, sub-0.5 ns switching, less sensitive to the pulses’ properties.

With CMOS device scaling slowing down, exploring new devices' working principles becomes paramount. The electron spin, as a complement to the charge, attracts much attention. The electron spin is characterized by the two well-defined projections on a given axis and is suitable for digital applications. Magnetic tunnel junctions (MTJs) feature different resistances in parallel and antiparallel magnetization configuration and enable spin-based types of non-volatile magnetic memories. MTJs are quite CMOS compatible as they are fabricated with a CMOS-friendly process. The relative magnetization configuration is manipulated by means of a spin-transfer torque (STT) acting on the free layer. The electrically addressable non-volatile STT memory is nearing mass production for stand-alone and embedded applications. The current status and modeling approaches of state-of-the art STT and spin-orbit torque memory are briefly reviewed.

A long-standing problem of magnetic field-free switching of a symmetric perpendicular free layer by spin-orbit torque is resolved by employing two perpendicular consecutive current pulses. The optimal overlap of the second pulse line is found to be around 50%. The robustness of switching with respect to fluctuations of the second current pulse duration and of the overlap with the free layer is demonstrated.

The spin orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is suited for applications in caches. However, its development is still hindered by relatively high switching currents in in-plane magnetized structures and the need of an external magnetic field for deterministic switching of perpendicular layers. We employ the two-pulse switching scheme to achieve deterministic sub-500ps and field-free switching in in-plane cells with weak perpendicular anisotropy and perpendicular rectangular structures.

We demonstrate that the spin-orbit torques generated by two orthogonal consecutive current pulses enable reliable and deterministic switching of a perpendicularly magnetized free magnetic layer without applying an external magnetic field. The switching current can be reduced by allowing the wire through which the second pulse is delivered to overlap only partly with the free layer. Surprisingly, the partial overlap makes the switching faster and 100% robust.

The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. It is particularly promising to employ non-volatility in IoT and automotive applications, as well as in the main computer memory as a replacement of conventional volatile CMOS-based DRAM. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structure with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents. Several paths to reduce the switching current in an in-plane SOT-MRAM structure are analyzed. The switching by means of two orthogonal current pulses complemented with an interface-induced perpendicular magnetic anisotropy allows reducing the switching current significantly for achieving sub-500ps switching.

Continuous miniaturization of semiconductor devices has been the main driver behind the outstanding increase of speed and performance of integrated circuits. In addition to a harmful active power penalty, small device dimensions result in rapidly rising leakages and fast growing stand-by power. The critical high power consumption becomes incompatible with the global demands to sustain and accelerate the vital industrial growth, and an introduction of new solutions for energy efficient computations becomes paramount. A highly attractive option to reduce power consumption is to introduce non-volatility in integrated circuits. Preserving the data without power eliminates the need for refreshment cycles and related leakages as well as the necessity to initialize the data in temporarily unused parts of the circuit. Spin transistors are promising devices, with the charge-based functionality complemented by the electron spin. The non-volatility is introduced by making the source and drain ferromagnetic. Recent advances in resolving several fundamental problems including spin injection from a metal ferromagnet to a semiconductor, spin propagation and relaxation, as well as spin manipulation by the electric field, resulted in successful demonstrations of such devices. However, the small relative current ratio between parallel/anti-parallel source and drain alignment at room temperature remains a substantial challenge preventing these devices from entering the market in the near future. In contrast, a magnetic tunnel junction is an excellent candidate for realizing power-reducing approaches, as it possesses a simple structure, long retention time, high endurance, fast operation speed, and yields high integration density. Magnetic tunnel junctions with large magnetoresistance ratio are perfectly suited as key elements of non-volatile magnetoresistive memory compatible with the complementary metal-oxide-semiconductor technology and capable to replace dynamic and potentially static random access memories. We review the present status of the technology, remaining challenges, as well as approaches to resolve the remaining problems. Regarding active power reduction, delegating data processing capabilities into the non-volatile segment and combining non-volatile elements with CMOS allows for efficient power gating. It also paves the way for a new low-power and high-performance computing paradigm-based on an intrinsic logic-in-memory architecture, where the same non-volatile elements are used to store and to process the information.

Nowadays there are two big obstacles for further progress in CMOS device technology. The energy dissipation due to leakage and the energy required to copy information between memory and processor. Even though cutting the power of unused circuits reduces the leakage dissipation to zero, it causes the loss of the locally stored information. Thus, it must be copied back from memory, when the circuit is turned on again. This, unfortunately, degrades the already strained available bandwidth between memory and processor. Using non-volatile elements which can serve as memory and information processing units is an attractive path to overcome these limitations in future computation environments. Therefore, we propose non-volatile circuits based on magnetic flip flops and non-volatile shift registers that extensively exploit these features. For the copy operation of the shift register we have proposed to traverse an unpolarized current through a portion of the read flip flops' free layer to create a spin polarized magnetization orientation encoded current and pass it to a subsequent free layer. There it exerts a spin-transfer torque and switches with the aid of a second clocked spin-transfer torque the subsequent layer. In order to test the feasibility of the operation procedure we reduce the shift register to two flip flops and study all possible input and output combinations via extensive simulations. We found that the switching behaves exactly as required for the proposed copy operation. Thus the feasibility of the operation as well as the operationability of the shift register are demonstrated.

Spin-dependent resonant tunneling in ferromagnet-oxide-semiconductor structures is currently of great interest due to the promising potential of semiconductors and silicon in particular for spin-driven applications. Trap-assisted tunneling explains the larger than predicted signal in three-terminal spin-injection experiments. However, for realistic comparison to experiments at elevated temperatures the master equation describing the occupation and spin evolution at an electron trap coupled to the contacts must be augmented to include spin relaxation and dephasing. A short spin relaxation time suppresses the “spin blockade”, thus reducing the magnetoresistance modulation. However, intensive dephasing does not strongly affect the magnetoresistance. The substantial magnetoresistance modulation is present at an arbitrary trap position relative to the contacts. Finally, an unusual non-monotonic dependence of the magnetoresistance half-width as a function of the perpendicular magnetic field with dephasing increased is observed.

We propose a new method of soft magnetic layer switching based on torques generated by the spin Hall effect and show a possibility of building 1Transistor-1MTJ cells with different paths for read and write operations. By performing extensive micromagnetic modeling our switching method has been verified.

The introduction of non-volatile elements into state-of-the art computing systems is a promising way to circumvent power dissipation and interconnection delay bottlenecks. This led us to the proposal of a non-volatile magnetic flip flop which offers high integration density as well as CMOS compatibility by not only acting as an auxiliary memory element but also carrying out the actual computation in the magnetic domain without relying on additional CMOS components. However, the required switching energy is still relatively high which results in a high current density needed for the flip flop manipulation. Here, we propose a modified device structure with a different device operation principle to benefit from the spin Hall effect in order to reduce the required switching energy without degrading other important parameters like switching speed or device reliability. Our results show that the use of the spin Hall effect is rewarded by a simultaneous reduction in switching time (×5 − ×2) and switching energy (×5 − ×1.6).

The electron spin properties are promising for future spin-driven devices. In contrast to charge, spin is not a conserved quantity, and having sufficiently long spin lifetime is critical for applications. Silicon, the major material of microelectronics, also appears to be a perfect material for spintronic applications. The peculiarities of the subband structure and details of the spin propagation in ultra-thin silicon films in the presence of strain are investigated. The application of an uniaxial stress can lift the degeneracy between the remaining two valleys in a (001) silicon film. The [001] equivalent valley coupling through the Γ-point, which results in a subband splitting in a confined relaxed electron structure, is properly included. Its impact on the shear strain inflicted equivalent subband splitting is evaluated, and thereby the dependence of spin lifetime on the valley splitting is predicted. In all possible conditions, the spin lifetime is observed to be boosted by several orders of magnitude.

The electron spin properties are promising for future spin-driven applications. Silicon, the major material of microelectronics, also appears to be a perfect material for spintronic applications. The peculiarities of the subband structure and details of the spin propagation in ultra-thin silicon films in presence of the spin-orbit interaction and strain are investigated. The application of shear strain dramatically reduces the spin relaxation in such films. We investigate in detail, how spin injection in any arbitrary direction modifies the spin relaxation matrix elements, and finally the spin lifetime in the samples. We demonstrate a two-fold enhancement of spin lifetime, when spin is injected in-plane of the sample, compared to that, when injected along the perpendicular-plane direction.

Silicon is perfectly suited for spin-driven applications. Recent progress and challenges regarding CMOS-compatible spin-based devices are reviewed. A realization of an intrinsic non-volatile logic-in-memory architecture in an MRAM array is demonstrated.

With CMOS technology rapidly approaching its scaling limits, the electron spin attracts much attention as an alternative degree of freedom for low-power applications. Silicon is suited for spin-driven applications because of its long spin lifetime. In confined electron systems the spin lifetime can be increased significantly by uniaxial stress. However, despite the many achievements, an experimental demonstration of a spin-based field effect transistor (SpinFET) is pending due to low spin injection efficiency and difficulties to manipulate spins electrically. This motivates researchers to look into CMOS-compatible spin-driven devices. Spin-transfer torque MRAM is fast, compact, and non-volatile; however, the high current for magnetization switching is a challenge. For in-plane magnetization a substantial reduction of the current is achieved, when the free layer is composed of two parts. In addition to information storing, the same MRAM cells can also be used for information processing, paving a path towards non-volatile logic-in-memory architectures.

The electron spin properties of semiconductors are of huge interest because of their potential for future spin-driven microelectronic devices. Modern charge-based electronics is dominated by silicon, and understanding the details of spin propagation in silicon structures is key for novel spin-based device applications. The peculiarities of the subband structure and details of the spin propagation in surface layers and thin silicon films in the presence of the spin-orbit interaction is under research. We investigate the influence of the spin injection direction on the spin relaxation. Beginning with the four-component wave functions, we show that the surface roughness induced spin intersubband relaxation matrix elements get reduced for an in-plane spin injection compared to perpendicular-plane spin injection, henceforth the corresponding spin relaxation rate (time) is diminished (enhanced). In order to explain this observation we point out that at the spin relaxation hot spots the perpendicular-plane spin injection results in a maximal spin randomization at any in-plane momentum, which increases the spin relaxation rate and decreases the spin lifetime as compared to an in-plane spin injection.

Recently, we proposed a non-volatile magnetic flip flop featuring a very small footprint. We studied its operational limits and current dependent characteristics. Since flip flops are commonly operated by clocked signals, their operation is time critical and the knowledge and understanding of their switching behavior is essential. In this work we study the dependence of the proposed flip flop on its device geometry. In order to facilitate the comparison to the previous results, the same device parameters are employed. The current density was fixed for both inputs at a value of 7 × 1010 A/m2, where all flip flops safely operated, and the free layers' dimensions were varied, independently. The free layer thickness was found as the most critical parameter affecting the switching time, followed by the layer length and a negligible dependence on width.

Oscillators belong to the group of fundamental building blocks and are ubiquitous in modern electronics. Especially spin torque nano oscillators are very attractive as cost effective on-chip integrated microwave oscillators, due to their nano-scale size, frequency tunability, broad temperature operation range, and CMOS technology compatibility. Recently, we proposed a micromagnetic structure capable of operating as non-volatile flip flop as well as a spin torque nano oscillator. The structure consists of three anti-ferromagnetically coupled stacks (two for excitation A, B and one for readout Q) and a shared free magnetic layer. Micromagnetic simulations show a current regime, where the structure exhibits large, stable, and tunable in-plane oscillations in the GHz range without the need of an external magnetic field or an oscillating current. In this work the dependence of these oscillations on the shared free layer geometry at a fixed input current is studied. It is shown that the precessional frequency can be controlled by the dimensions of the shared free layer. Most efficient is to utilize the layer thickness to control the precessional frequency, but also changing the layer length can be exploited.

Spintronics attracts much attention because of the potential to build novel spin-based devices which are superior to nowadays charge-based microelectronic devices. Silicon, the main element of microelectronics, is promising for spin-driven applications. We investigate the surface roughness and electron-phonon limited spin relaxation in silicon films taking into account the coupling between the relevant valleys through the Γ-point. We demonstrate that applying uniaxial stress along the [110] direction considerably suppresses the spin relaxation.

Memories based on charge storage are gradually approaching the physical limits of scalability. Magnetoresistive random access memory (MRAM) with spin-transfer torque (STT) is a promising candidate for future universal memory. However, the reduction of the switching current density and/or switching time while maintaining high thermal stability are the main challenges of this memory cell. A substantial decrease of the switching time in in-plane magnetic tunnel junctions is achieved by a special design of the free magnetic layer. The scaling potential of this cell based on the thermal stability analysis is discussed. The designed non-volatile memory cell is promising for STT-MRAM arrays. Introducing non-volatility into logic circuits is critical to reduce the standby power and enable instant-on applications. Recently, circuits containing MRAM cells for logic were presented. The logic operations are implemented by using reprogrammable- and implication-based magnetic tunnel junction (MTJ) logic gates providing a new intrinsic logic-in-memory computational platform. A critical analysis of possible tradeoffs in different designs of stateful logic architectures is presented. The analysis indicates that MRAM-based logic is a well suited for high performance parallel non-volatile computations.

Introducing non-volatility into CMOS circuits is a promising solution to overcome the standby power dissipation due to leakage, which has become a major challenge of today's VLSI. Stateful logic inherently realizes non-volatile logic-in-memory circuits with zero-standby power and opens the door for a shift away from the Von Neumann architecture. To ensure a correct logic behavior in all input patterns, the reliability of the conditional switching in the stateful logic gates is the most important design objective. In this work the goal is to efficiently calculate the reliabilities in TiO 2 -based and spintronic stateful implication (IMP) logic gates with the aid of compact but sufficiently accurate device models. It is demonstrated that in order to avoid a state computation error in the TiO 2 -based IMP gate, refreshing is required after a limited number of logic steps as the state drift errors accumulate. Due to the magnetic bistability of the magnetic tunnel junctions (MTJ), spin-transfer torque (STT)-MTJ-based IMP logic gates eliminate error accumulation and thus are inherently suited for digital computing. A modified SPICE model is presented to optimize the circuit parameters of the STT-MTJ-based gates for providing a reliable conditional switching behavior.

The breathtaking increase in performance of integrated circuits is supported by the continuous miniaturization of CMOS devices. However, growing technological challenges and soaring costs are gradually bringing scaling to an end, and research on alternative technologies and computational principles becomes important. Spin attracts attention as alternative to the charge degree of freedom for computations and non-volatile memory applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Special attention is paid to methods for enhancing the electron spin lifetime in silicon inversion layers and thin films necessary for realizing spin-based field-effect transistors. A new rapidly switching structure for spin-based non-volatile memory cell, MRAM, was optimized by means of micromagnetic simulations. Several memory cells can be assembled in logic gates capable to perform logic operations. We demonstrate that an implication gate is promising for realizing intrinsic non-volatile logic-in-memory architectures.

Static power due to the leakage currents has become a major concern in CMOS logic circuits as the technology is scaled down. Introducing non-volatility into logic circuits is a promising solution offering zero standby power and instant-on applications. Recently, spin-transfer torque magnetoresistive random-access memory (STT-MRAM) circuits have been presented to enable stateful logic by implementing reprogrammable- and implication-based magnetic tunnel junction logic operations. In this work we describe tradeoffs in the design of MRAM-based stateful logic architectures. It has been shown that although the implication logic outperforms the reprogrammable architecture, a combination of these two architectures reduces the number of required logic steps and the energy consumption, however, at the cost of reduced reliability. MRAM-based logic is also well suited for high performance parallel non-volatile computations as it is shown by an example.

Recently, we proposed an alternative non-volatile magnetic flip flop which allows high integration density. This work extends the up to now gained results to the devices’ functionality under statistically distributed magnetization variations of its free layer. Assuming position uncorrelated random fluctuations in the free layer, that the variations are fixed with respect to time, and that small deviations from its mean are more likely than big ones, a Gaussian distribution was chosen to model the random fluctuations. The random variations were added to the simulations as a position dependent Zeeman term and their influence was varied by changing the variance of the distribution scaled in percent of the free layers saturation magnetization. The results with and without thermal excitation show that the flip flop is capable of operating under high free layer field variations.

Electron spin attracts much attention as an alternative degree of freedom for low-power reprogrammable logic and non-volatile memory applications. Silicon appears to be the perfect material for spin-driven applications. Recent progress and challenges in simulating spin-based devices are briefly reviewed. Strain-induced enhancement of the electron spin lifetime in silicon thin films is predicted and its impact on spin transport in SpinFETs is discussed. A new design of the spin-based nonvolatile memory cell, MRAM, is presented. By means of micromagnetic simulations it is demonstrated that the new design leads to a reduction of the switching time of the cell. Any two memory cells from a MRAM array can form an implication logic gate. It is shown how by using these gates an intrinsic non-volatile logic-in-memory architecture is realized.

We investigate the surface roughness induced spin relaxation in scaled spin MOSFETs. We show that the regions in the momentum space, responsible for strong spin relaxation, can be efficiently removed by applying uniaxial strain. The spin lifetime in strained films can be improved by orders of magnitude, while the momentum relaxation time determining the electron mobility can only be increased by a factor of two.

A performance analysis and comparison of two one-transistor/one-magnetic tunnel junction (1T/1MTJ)-based logic gates is presented. The energy consumption as well as the reliability of different Boolean logic functions utilizing the two circuit topologies are studied and the adequacy of their employment for specific non-volatile logic applications is discussed. It has been shown that the implication logic design exhibits a more reliable behavior compared to the reprogrammable logic design featuring conventional Boolean logic operations like (N)AND and (N)OR. Although the comparison between the two error optimized logic gate types shows that the fundamental logic operations with the reprogrammable gates require less energy than with the IMP gates, the situation reverses for more complex Boolean logic operations.

We investigate the surface roughness and phonon induced spin and momentum relaxation in ultra-scaled SOI MOSFETs. We show that the spin-flip hot spots characterized by strong spin relaxation can be efficiently removed by applying shear strain resulting in an increase of spin lifetime by orders of magnitude. In contrast, the momentum relaxation time in ultrathin films, which is mostly determined by surface roughness scattering can be only increased by a factor of two, in agreement with strain-induced mobility enhancement data.

The ever increasing demand in fast and cheap bulk memory as well as electronics in general has driven the scaling efforts in CMOS since its very beginnings. Today, pushing the limits of integration density is still a major concern, but gradually power efficient computing gains more and more interest. A possible way to reduce power consumption is to introduce non-volatility into the devices. Thus power is consumed only, when information is written or read out, while the rest of the time the devices preserve the information with out any power demand. In this work we propose a novel non-volatile magnetic flip-flop which shifts the actual logic operation from the electric signal domain to the magnetic domain, operating via constructive and destructive superposition of spin waves generated by the spin transfer torque effect. Furthermore we carried out a rigorous simulation study for three different device sizes and found them operational between ≈4×1010A/m2 and ≈1012A/m2 at switching times from tens of nanoseconds to picoseconds.