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Recent studies suggest that cells make stochastic choices with respect to differentiation or division. The effect of molecule concentration on cell division rate is analysed in this work. However, the molecular mechanism underlying such stochasticity is unknown. Here, we computationally model the effects of molecule concentration (acts as noise) on the Hes1/miR-9 oscillator. Consequences of low molecular numbers of interacting species are determined experimentally by the researchers. We report that increased stochasticity spreads the timing of differentiation in a population, such that initially equivalent cells differentiate over a period of time. Surprisingly, inherent stochasticity also increases the robustness of the progenitor state and lessens the impact of unequal, random distribution of molecules at cell division on the temporal spread of differentiation at the population level. This advantageous use of biological noise contrasts with the view that noise needs to be counteracted.

Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Sub-threshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.

This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9 %.