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Particle filtering is very reliable in modelling non-Gaussian and non-linear elements of physical systems, which makes it ideal for tracking and localization applications. However, a major drawback of particle filters is their computational complexity, which inhibits their use in real-time applications with conventional CPU or DSP based implementation schemes. The re-sampling step in the particle filters creates a computational bottleneck since it is inherently sequential and cannot be parallelized. This paper proposes a modification to the existing particle filter algorithm, which enables parallel re-sampling and reduces the effect of the re-sampling bottleneck. We then present a high-speed and dedicated hardware architecture incorporating pipe-lining and parallelization design strategies to supplement the modified algorithm and lower the execution time considerably. From an application standpoint, we propose a novel source localization model to estimate the position of a source in a noisy environment using the particle filter algorithm implemented on hardware. The design has been prototyped using Artix-7 field-programmable gate array (FPGA), and resource utilization for the proposed system is presented. Further, we show the execution time and estimation accuracy of the high-speed architecture and observe a significant reduction in computational time. Our implementation of particle filters on FPGA is scalable and modular, with a low execution time of about $5.62~\mu \text{s}$ for processing 1024 particles (compared to 64 ms on Intel Core i7-7700 CPU with eight cores clocking at 3.60 GHz) and can be deployed for real-time applications.

We will demonstrate an FPGA implementation of an event- based vision sensor using a commercially available frame- based camera. The demonstration setup consists of the host PC that includes the Quartus Prime software which is used to program and configure the FPGA, a commercially available 8-megapixel MIPI (Mobile Industry Processor Interface) camera kit, and a Cyclone V DE10-nano FPGA board, as shown in Fig. 1. The camera kit has been used to capture conventional frame- based images [1]. It is mounted on the FPGA board via the 2×20 pin general-purpose input-output port connector interface of the FPGA board. The FPGA board is used to process the digital pixel data, which are received from the camera, and to generate events. The generated events are displayed on a VGA monitor with predefined colors for each event behavior.

The recent popularity of indoor-localization applications such as secure access and asset tracking has led to growing interest in accurate RF-based ranging solutions. Impulse-radio ultra-wideband (IR-UWB) is a promising solution for accurate ranging due to its wideband 0peration. The recently released IEEE 802. 15.4z standard [1] improves upon the security of ranging and mandates a coherent operation with higher mean pulse-repetition frequencies (mPRF), in comparison to the legacy standard IEEE 802. 15.4a. The next generation IR-UWB devices demand ultra-low-power operation while meeting the strict spectrum regulations to operate worldwide in C and X bands (4 to 10GHz). The prior-art coherent IR-UWB transmitters either consume very high power [2] or result in high spurious emissions in adjacent channels due to poor sidelobe suppression [3 –6]. In this work, an asynchronous polar transmitter is proposed that consumes 4.9mW active power with an output power spectral density (PSD) of -41.3dBm/MHz and a sidelobe suppression of over 28dBrin IEEE 802. 15.4zl24.8MHzmPRF mode, channel 9 (7987.2MHz). Further, we demonstrate the use of an injection-locked ring oscillator (IL-R0) with fine-grained duty-cycling of the TX chain to achieve state-of-the-art power consumption for mPRFs from 3.9MHz to 124. 8MHz while maintaining coherent operation over the packet.

Nowadays, almost every mobile device features Bluetooth Low Energy (BLE) connectivity. Accurate RF-based ranging is of major importance to enable rapidly emerging applications such as indoor localization and navigation, asset tracking as well as secure access control. Phase-based ranging has many advantages over other methods such as Time-of-Flight or signal-strength-based approaches [1]. Phase-based ranging is based on the phase difference between the two nodes, which depends on the RF frequency. To mitigate multipath problems and deal with the 2n ambiguity in phase measurements, the phase difference is measured on multiple frequencies, i.e. Multi-Carrier Phase Difference (MCPD) [1].

Batch-normalization (BN) layers are thought to be an integrally important layer type in today's state-of-the-art deep convolutional neural networks for computer vision tasks such as classification and detection. However, BN layers introduce complexity and computational overheads that are highly undesirable for training and/or inference on low-power custom hardware implementations of real-time embedded vision systems such as UAVs, robots and Internet of Things (IoT) devices. They are also problematic when batch sizes need to be very small during training, and innovations such as residual connections introduced more recently than BN layers could potentially have lessened their impact. In this paper we aim to quantify the benefits BN layers offer in image classification networks, in comparison with alternative choices. In particular, we study networks that use shifted-ReLU layers instead of BN layers. We found, following experiments with wide residual networks applied to the ImageNet, CIFAR 10 and CIFAR 100 image classification datasets, that BN layers do not consistently offer a significant advantage. We found that the accuracy margin offered by BN layers depends on the data set, the network size, and the bit-depth of weights. We conclude that in situations where BN layers are undesirable due to speed, memory or complexity costs, that using shifted-ReLU layers instead should be considered; we found they can offer advantages in all these areas, and often do not impose a significant accuracy cost., Comment: 8 pages, published IEEE conference paper

We present Rogue In-flight Data Load (RIDL), a new class of speculative unprivileged and constrained attacks to leak arbitrary data across address spaces and privilege boundaries (e.g., process, kernel, SGX, and even CPU-internal operations). Our reverse engineering efforts show such vulnerabilities originate from a variety of micro-optimizations pervasive in commodity (Intel) processors, which cause the CPU to speculatively serve loads using extraneous CPU-internal in-flight data (e.g., in the line fill buffers). Contrary to other state-of-the-art speculative execution attacks, such as Spectre, Meltdown and Foreshadow, RIDL can leak this arbitrary in-flight data with no assumptions on the state of the caches or translation data structures controlled by privileged software. The implications are worrisome. First, RIDL attacks can be implemented even from linear execution with no invalid page faults, eliminating the need for exception suppression mechanisms and enabling system-wide attacks from arbitrary unprivileged code (including JavaScript in the browser). To exemplify such attacks, we build a number of practical exploits that leak sensitive information from victim processes, virtual machines, kernel, SGX and CPU-internal components. Second, and perhaps more importantly, RIDL bypasses all existing 'spot' mitigations in software (e.g., KPTI, PTE inversion) and hardware (e.g., speculative store bypass disable) and cannot easily be mitigated even by more heavyweight defenses (e.g., L1D flushing or disabling SMT). RIDL questions the sustainability of a per-variant, spot mitigation strategy and suggests more fundamental mitigations are needed to contain ever-emerging speculative execution attacks.

We propose a biologically inspired binaural sound localization system using a deep convolutional neural network (CNN) for reverberant environments. It utilizes a binaural Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear system to analyze binaural signals, a lateral inhibition function to sharpen temporal information of cochlear channels, and instantaneous correlation function on the two cochlear channels to encode binaural cues. The generated 2-D instantaneous correlation matrix (correlogram) encodes both interaural phase difference (IPD) cues and spectral information in a unified framework. Additionally, a sound onset detector is exploited to generate the correlograms only during sound onsets to remove interference from echoes. The onset correlograms are analyzed using a deep CNN for regression to the azimuthal angle of the sound. The proposed system was evaluated using experimental data in a reverberant environment, and displayed a root mean square localization error (RMSE) of 3.68° in the −90° to 90° range.

A digital polar PA for LTE-based cellular Internet of Things (CIoT) is presented. It features a class-G back-off efficiency enhancement, using only one single supply. The PA consists of a number of parallel switched-capacitor (SC) cells. Each cell can be configured in two output-power modes, using only a single supply. At 807MHz, the peak output power is 27.1dBm, with an efficiency (PAE) of 33.3%. The efficiency at −6dBps and −12dB ps is 22.5% and 14.4% respectively, which is an improvement of 1.3x and 1.7x compared to class-B. The 13-bit resolution enables a power-control range for Cat-M1 and Cat-NB1 signals of >63dB. In that range, the EVM is

We propose a biologically inspired binaural sound localization system for reverberant environments. It uses two 100-channel cochlear models to analyze binaural signals, and each channel of the left cochlea is compared with each channel of the right cochlea in parallel to generate a 2-D instantaneous correlation matrix (correlogram). The correlogram encodes both binaural cues and spectral information in a unified framework. A sound onset detector is used to generate the correlogram only during the sound onsets, and the onset correlogram is analyzed using a linear regression approach as well as an extreme learning machine (ELM). The proposed system is evaluated using experimental data in reverberation environments, and we obtained an average absolute error of 16.5° for linear regression and 12.8° for ELM regression in the −90° to 90° range.

Filters in cochlea models use different coefficients to break sound into a two-dimensional time-frequency representation. On digital hardware with a single sampling rate, the number of bits required to represent these coefficients require substantial computational resources such as memory storage. In this paper, we present a cochlea model operating at multiple sampling rates. As a result, fewer bits are required to represent filter coefficients on hardware as opposed to all the filters operating at a single sampling rate. Additionally, with a 108-filter cochlea implementation, up to nine times fewer coefficients are used than a single sampling rate approach across all filter sections. We present an implementation of 108 filters in Matlab and on an Altera Cyclone V FPGA with a low logic level utilization of 2.57%. Our model can thus be extended to include other auditory processing models such as loudness, pitch perception and timbre recognition on a single FPGA.

In previous research, the application of sub-threshold electrical nerve stimulation (SENS) to peripheral nerves has been shown to improve tactile sensitivity. SENS has applications in the symptomatic treatment of a wide array of conditions that result in the loss of peripheral nerve function. These include diabetes, stroke, and age related peripheral neuropathy. The technology is dependent on careful control of the amplitude of the intervention stimulation relative to the user's perception threshold. However, little is known about the factors that influence the perception threshold and whether it can be treated as a constant. Here we present a study where we applied a two alternate forced choice paradigm to determine electrical perception threshold. We investigated participant, noise frequency characteristics, electrode location, electrode type, and electrode impedance characteristics as explanatory factors for the variability seen in the threshold outcome. We find that the electrical perception threshold is dependent on the frequency characteristics of the signal applied, but varies widely without correlation to the remaining variables. It was also highly variable when re-tested under identical conditions. Our results cast doubt on the ability to treat the electrical threshold as a single value that holds constant for a particular participant and electrode placement. This finding has significant implications in SENS applications.

The MNIST dataset has become a standard benchmark for learning, classification and computer vision systems. Contributing to its widespread adoption are the understandable and intuitive nature of the task, the relatively small size and storage requirements and the accessibility and ease-of-use of the database itself. The MNIST database was derived from a larger dataset known as the NIST Special Database 19 which contains digits, uppercase and lowercase handwritten letters. This paper introduces a variant of the full NIST dataset, which we have called Extended MNIST (EMNIST), which follows the same conversion paradigm used to create the MNIST dataset. The result is a dataset that constitutes a more challenging classification task involving letters and digits, and one that shares the same image structure and parameters as the original MNIST task, allowing for direct compatibility with all existing classifiers and systems. Benchmark results using an online ELM algorithm are presented along with a validation of the conversion process through the comparison of the classification results on NIST digits and the MNIST digits.

We present a stochastic Bayesian neuron (SBN) that codes for a binary hidden variable and the temporal dynamics of which can be explained as a Bayesian inference. We show that our SBN combines the maximum likelihood of its synaptic inputs and the prior probability of the hidden variable to infer the presence of the hidden variable. Probabilistic models are computationally complex, which makes them difficult to implement using standard state-of-the-art digital implementation. Here, we employ stochastic logic elements to implement the SBN using minimum hardware resources. The SBN could be used as a basic element to develop a Bayesian processor that works on probability instead of deterministic logic.

In the mammalian auditory pathway, the cochlea is the first stage of processing where the incoming sound signal is mapped into various frequency channels. This multi-channel output contains subtle spectrotemporal features essential in sound source identification and segregation. These features have a large dynamic range. They have a large gain and sharp tuning at low sound levels, and a low gain and broad tuning at high sound levels. These properties are inherent in the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) model of the cochlea. The CAR segment of the model simulates the basilar membrane's response to sound while the FAC segment simulates hair cells and sub-cortical responses resulting in a neural activity pattern necessary for sound perception analysis. We have previously implemented the CAR model on an FPGA, and in this paper, we implement the complete CAR-FAC model with 100 sections on an FPGA for a sample rate of 32 kHz. The FAC part includes outer and inner hair cell algorithms incorporating nonlinearity as well as an automatic gain control for modulating basilar membrane output with respect to input sound levels. We have implemented our design using time-multiplexing approach, where hardware resources of one cochlea section are reused for all the 100 sections of the model.

In the last decade, computational neuroscience and machine learning communities have witnessed the emergence of several algorithms where an input signal is randomly projected to a higher dimensional space via a nonlinear activation function. These methods are increasingly popular for regression or classification tasks, but this kind of neural network has remained difficult to implement efficiently in hardware. This is partly due to the all-to-all connectivity required between the input and hidden layers in these networks. The concept of using receptive fields (RF) for classification tasks stems from biology, in which sensory neurons often respond to a limited spatial range of the input stimulus. Incorporating this methodology into a classification system often yields an increase in performance. This paper presents an SRAM-based implementation of the RF approach to implement this kind of neural network on hardware. Since SRAM has a much smaller footprint compared to logic gates, this implementation is much more efficient in terms of hardware resources. The system was implemented and verified on an FPGA to demonstrate the efficiencies and flexibility of this approach for MNIST digit recognition task.

A 2.4GHz transceiver SoC, operating at minimum 0.9V, is presented as a power-efficient and cost-effective solution for the coming Internet of Things (IoT) platform. The transceiver is compliant with Bluetooth Low Energy (BLE) 4.0/4.2/5.0 PHY and 802.15.4 standards. The measured sensitivity is −93dBm at 1V, and TX output power is 1dBm. Direct battery attachment is feasible, due to the 1.5µW deep-sleep power which enables µW-range average power consumption without Low Drop-Out (LDO) regulator. The radio is fabricated in 40nm CMOS technology.