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In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage $({\mathrm { V}}_{\mathrm { T}})$ fluctuations induced by traps and show that lower values for the average and rms ${\mathrm { V}}_{\mathrm { T}}$ arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.

In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.

The hardware implementation of neuromorphic system requires energy and area-efficient hardware. Memristor-based hardware architectures is a promising approach that naturally mimics the switching behavior of the neuron models. However, to build complex neural systems, it is a tedious process to select the right memristor models and architectures that are suitable to be used in a range of realistic conditions. To simplify the design and development of neuromemristive architectures, we present a web-based graphical user interface (GUI) called “PyMem” that uses Keras Python to implement multiple memristor models on multiple neural architectures that can be used to analyze their working under a wide range of hardware variability. Without the need for programming, the GUI provides options for adding variability to the memristors and observing the neural network behavior under realistic conditions. The tool has options to characterize the ideal (software) and nonideal (hardware) for performance analysis including accuracy, precision, recall, and relative current error values.

In this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( $V_{\text {t}}$ ) to be adjustable (i.e., low- $V_{\text {t}}$ and high- $V_{\text {t}}$ states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.

Ensuring a timing guarantee is crucial for time-critical applications. However, this task becomes more challenging with the increasing performance variability generated by complicated modern hardware and software. A widespread solution to the problem is real-time scheduling, which depends on worst-case execution time (WCET) and dynamic voltage frequency scaling (DVFS). Although these techniques provide the necessary guarantees, they also exhibit important limitations from the long switching time of DVFS and the overly pessimistic execution time model of WCET. In this work, a multitimescale mitigation methodology is proposed to improve the way of tackling performance variability in both timing guarantee and energy saving. By using both the DVFS and heterogeneous datapath (HDP) knobs, this methodology can push the timescale of mitigation down to the submillisecond level. Moreover, this methodology can calculate a tight upper bound of execution time at run-time using dynamic scenarios (DSs). Simulation shows that the proposed methodology can ensure zero deadline misses with a smaller safety time margin than the method using only DVFS and WCET. This advantage can translate into an energy reduction by half compared to the conventional WCET-based method with a single DVFS knob. [ABSTRACT FROM AUTHOR]

Massive proliferation of Variable Energy Resources (VERs) in modern power systems has posed a variety of challenges to the reliable operation of the power grid and has, at times, jeopardized the system flexibility. Flexibility is the system’s ability to respond to and cope with the imbalances between supply and demand while managing the uncertainty and variability of VERs and maintaining the power system’s security and reliability within the acceptable margins. Leveraging the system’s available resources and capabilities, the system operators must take strategic actions to mitigate the impacts of VERs on the grid flexibility at a reasonable cost. The concept of flexibility is somewhat novel, which calls for profound studies and analyses to address different aspects of flexibility, but not limited to definition and characterization of standard metrics and indices to measure the power grid flexibility, flexibility-centred operation and planning models for the power grid, etc. This paper provides a comprehensive review of the state-of-the-art research on power system flexibility, including existing definitions and quantification measures, flexible resources, and flexibility products and services in electricity markets.

In this work, we report the impact of source region’s random dopant fluctuations (RDFs) induced variability on n-type silicon double gate (DG)-TFETs via 3D-device simulation. We have observed that source region’s RDF induces strong variability in the analog and RF figures of merit (FOMs) of the devices. This is the first report showing detailed impact of RDF on DG-TFET device and based circuit. The impact of RDF is analyzed by taking RDF only in source region as tunneling barrier width depends mostly on source doping and so does the ON-state current. The variation of analog and RF FOMs, such as transconductance $({g}_{m})$ , transconductance generation factor $({g}_{m}/{I}_{d})$ , output resistance $({R}_{o})$ , intrinsic gain $({g}_{m}{R}_{o})$ , capacitances $({C}_{{gs}}$ , ${C}_{{gd}}$), gate delay $({T}_{m})$ , cutoff frequency $({f}_{T})$ , and subthreshold swing (SS), is reported. We benchmark the device analog and RF performance of the RDF sample with respect to continuum one. On the basis of observed effective deviation in characteristics, common-source amplifier circuit is simulated to analyze the deviation in voltage-transfer characteristic (VTC) and gain–bandwidth product (GBWP). [ABSTRACT FROM AUTHOR]

HfO2-based FeFET is a remarkably promising candidate among emerging memory technologies. Its manifold applications range from nonvolatile memory to neuromorphic computing. However, the memory window (MW) is limited, since the ferroelectric properties of HfO2 degrade with increased ferroelectric thickness. Recent developments in asymmetric double-gate FeFET with dual port boast of a large MW when read from the back gate (BG), compared with the front gate (FG). It has been predicted that this can qualify as an excellent candidate for multi-level-cell (MLC) storage due to its high MW. However, the variability of the intermediate threshold voltage (VTH) states must be within reasonable limits to enable error-free reliable operation. In this work, we have thoroughly investigated the variability of VTH states in dual-port FeFET due to the random spatial distribution of ferroelectric domains. We have also accounted for the conventional sources of device variations, such as random dopant fluctuation (RDF), metal work-function variation (WFV), and line edge roughness (LER). We show that as MW is amplified when reading from BG compared with FG, variability is also amplified, thereby restricting its usage to accommodate a higher number of states. Nevertheless, a key benefit of BG read stems from the ability to reduce the ferroelectric thickness (tFE) from 10 nm down to merely 3 nm, still retaining an MW of 2.7 V. Notably, reducing tFE makes it possible to operate the FeFET at a lower voltage (1.8 V instead of 4 V). This creates avenues for better compatibility with the existing VLSI designs and reliability enhancements. We demonstrate that the variations in VTH are reduced for BG read on reducing tFE, which allows us to hold the same number of states even at such a scaled thickness. Finally, we predict the maximum number of states (in terms of bits) that can be stored and read reliably in dual-port FeFET for FG read and BG read at nominal and scaled tFE. We demonstrate that dual-port FeFET with BG read and scaled tFE offers MLC storage of 3 bits. [ABSTRACT FROM AUTHOR]

The correlation between percolation paths and hot-carrier degradation (HCD) in FinFETs is first presented in this work. Metal grain granularity (MGG) and random dopants (RD) influence on percolation paths is explored, and the conclusions are expanded to any source of potential fluctuations. All the analyses are performed using a 3-D TCAD Monte Carlo device simulator, in which carrier-ion and carrier-carrier interactions are treated in real-space, including the individual impact of localized charges. The carriers’ energy bidimensional probability distribution is shown to follow the percolation paths for carriers with both low and high energy, the former being more pronounced near the source and the latter concentrated on the drain end. This suggests that HCD is more pronounced on the regions in the vicinity of percolation paths. Trapped charge’s impact is also shown to be more significant when the trap is located near percolation paths, reinforcing the impact of hot carrier degradation. The analysis performed in this work may be used as the basis of a comprehensive HCD model, which is imperative for state-of-the-art FinFETs. [ABSTRACT FROM AUTHOR]

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps. [ABSTRACT FROM AUTHOR]

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, ${\mathrm {FoM}}_{A}$ , is 209 dBc/Hz. [ABSTRACT FROM AUTHOR]

Memristor crossbar architecture is one of the most popular circuit configurations due to its wide range of practical applications. The crossbar architecture can emulate the weighted summation operation, called multiply and accumulate operation (MAC). The errors to MAC computing get introduced due to a range of crossbar variability. We broadly group the variability in three categories: (1) device-to-device variations, (2) programming nonlinearity, and (3) those from peripheral circuits. This tutorial provides insights into the variability and compensation approaches that can be adopted to reduce its impact when designing for practical applications with crossbars. [ABSTRACT FROM AUTHOR]

An accurate and efficient noise-based simulation technique for predicting the impact of device-parameter variability on the DC statistical behavior of integrated circuits is presented. The proposed method is validated on a source follower, a diode-load inverter and a current mirror based on organic thin-film transistors. Taking advantage of the standard noise analysis of a circuit, after translating the statistical variation of the electrical parameters of the transistors into equivalent-noise circuit components, the proposed technique yields results identical to those obtained from a Monte Carlo simulation, but in a significantly shorter amount of time.

Steganography algorithms hide the secret message in the cover image and provide imperceptibility to the attacker. The Least Significant Bit (LSB) algorithm is the preferred data hiding method. In this method, the least significant bit of the cover image pixel is substituted with the secret data bit. However, this method provides high variability if k-LSB bits of the cover image is replaced with secret data bit. To reduce the variability, various optimization algorithms are deployed in image steganography. These algorithms search the optimal pixels in the cover image, and data hiding is performed using the k-bits LSB method. Several iterations of optimization algorithms have increased the time complexity upon achieving this goal. Therefore, in this paper, a data hiding approach is designed based on the flipping approach that reduces variability and provides lesser time complexity. In the proposed method, initially, data hiding is performed using the k-bit LSB method in the cover image, and stego image is obtained. After that, the absolute difference between the cover and stego image is determined and compared with the threshold value. If the absolute difference is higher than the threshold value, then the adjacent bit of the k-bit LSB method is flipped. This process reduces the variability because flipping the adjacent bit will make the pixel value of the stego image closer to the cover image. The simulation evaluates using various performance metrics upon testing on standard dataset images. The simulation results show that the proposed method provides lesser variability, good visual quality, lesser time complexity than Genetic and Bayesian Optimization algorithms and the existing flip method.

To estimate characteristic fluctuation of emerging devices, three-dimensional device simulation has been performed intensively for various random cases; however, it strongly relies on huge computational resources. In this paper, we report a nanosized-metal-grain pattern-dependent model by using the method of multi-variable non-linear regression (MVNLR) for the threshold voltage fluctuation ( $\sigma \text{V}_{\mathrm {th}}$ ) of gate-all-around silicon nanowire metal-oxide-semiconductor field-effect transistors. The model is developed by perturbing the local metal grains of specific patterns and summing up each metal grain of various grain patterns. The method of MVNLR is applied to build equations for nominal devices, and devices with high work-function (WK) and low WK with respect to process parameters (radius of channel, gate length, channel doping, and oxide thickness), which are generated by the design of experiments. The proposed model can estimate the magnitude of $\sigma \text{V}_{\mathrm {th}}$ accurately (error rate < 1%) for all parameters, where an error-correction process is further adopted by using a simplified one-perceptron method.

One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO2 layer within the HfO2 switching layer, these variations can be significantly reduced. The TiN/HfO2/SnO2/HfO2/Pt material stack achieves ~ 10 times smaller standard deviation for the high resistance state($>100\text{k}\Omega $) cycle to cycle distribution compared with the control group without the SnO2 layer. The tight high resistance state distribution retained after 107 pulse cycling. Incremental RESET pulse measurement indicates that the thin SnO2 acts as an oxygen stopping layer and thus explains the origin of reduced variability. The concept of an oxygen stopping layer is promising for reducing variability for resistive memory. [ABSTRACT FROM AUTHOR]

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with $\sigma ~{V}_{T}$ values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ($\sigma {V}_{T}$ = 8 mV) and minimally influenced by the GER ($\sigma {V}_{T} \approx 4$ mV). The variability of NS FETs makes them strong candidates to replace FinFETs. [ABSTRACT FROM AUTHOR]

Fast and stable switching between states is one of the key factors for the success resistive random access memory (RRAM) development. In an array, wide reset efficiency variation in RRAM cells is found to link to the characteristics of its low frequency noise (LFN) in bit-cell current. Through Monte Carlo simulation on randomly placing conductive filaments (CF), LFN characteristics correspond to the densities of the CF in the RRAM film. Further correlations between LFN features and the reset efficiency are found. In addition, CF topography are found to change after long term cycling tests. A trimming process is proposed to minimize the impacts of stochastic CF generation, leading to increase reset speed.

Cyber-Physical System (CPS) is co-engineered interacting networks of physical and computational components that operate on different spatial and temporal scales. The safety goal of a single CPS is usually achieved by applying hazard analysis techniques and by following the standard processes defined in ISO 26262 and IEC 61508. However, the safety property may not be satisfied when multiple CPSs collaborate due to complexity, uncertainty, and variability. Therefore, a technique that would provide a hazardous-free collaboration for multiple CPSs is required to preserve sustainability. In this paper, we analyze the hazards arising due to variabilities in collaborative CPSs. We extend the hazard analysis techniques (FTA, FMEA, and ETA) to explore hazards with variability and developed a fault traceability graph from our extended techniques to trace the faults considered by multiple hazard analyses in collaborative CPSs with variability. To justify our proposed approach, a case study on the human rescue robot system was conducted to analyze hazards emerging as a result of variabilities. Finally, a tool (CPS Tracer) was developed to model the FTA, ETA, and FMEA with variability (v_FTA, v_FMEA, and v_ETA). It also and generates the fault traceability graph (v_FTG) that represents fault propagation route.

A machine learning (ML) model by combing two autoencoders and one linear regression model is proposed to avoid overfitting and to improve the accuracy of Technology Computer-Aided Design (TCAD)-augmented ML for semiconductor structural variation identification and inverse design, without using domain expertise. TCAD-augmented ML utilizes TCAD simulations to generate sufficient data for ML model development when experimental data are inadequate. The ML model can then be used to identify semiconductor structural variation for given experimental electrical measurements. In this study, the variation of layer thicknesses in the p-i-n diode is used as a demonstration. An ML model is developed to predict the diode layer thicknesses based on a given Current-Voltage (IV) curve. Although the variations of interest can be incorporated easily in TCAD simulations to generate ML training data, the TCAD-augmented ML model generally is overfitted and cannot predict the variations in experiment well due to hidden variables which also alters the IV curves. We show that by using an autoencoder, this problem can be solved. To verify the effectiveness, another set of TCAD simulation data is generated with hidden variables (dopant concentration variation) to emulate experimental data. Testing on the second set of data shows that the proposed model can avoid overfitting and has up to 15 times improvement in accuracy in thickness prediction. Moreover, this model is used successfully to perform inverse design and can capture an underlying physics that cannot be described by a simple physical parameter.

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal–oxide–semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly. [ABSTRACT FROM AUTHOR]

This paper introduces a new approach to quantify the impact of forward propagated demand and weather uncertainty on power system planning and operation models. Recent studies indicate that such sampling uncertainty, originating from demand and weather time series inputs, should not be ignored. However, established uncertainty quantification approaches fail in this context due to the data and computing resources required for standard Monte Carlo analysis with disjoint samples. The method introduced here uses an m out of n bootstrap with shorter time series than the original, enhancing computational efficiency and avoiding the need for any additional data. It both quantifies output uncertainty and determines the sample length required for desired confidence levels. Simulations and validation exercises are performed on two capacity expansion planning models and one unit commitment and economic dispatch model. A diagnostic for the validity of estimated uncertainty bounds is discussed. The models, data and code are made available. [ABSTRACT FROM AUTHOR]

Spread spectrum time domain reflectometry (SSTDR) is a non-intrusive method for electrical fault detection and localization that enables continuous monitoring of live electrical systems. Electrical faults create changes in impedance that create subsequent changes in the SSTDR reflection response. These changes in reflection response can be detected only if the changes are outside the window of uncertainty of the SSTDR measurement. In this paper, we establish a method of determining this window of uncertainty and the associated minimum-detectable change in impedance for SSTDR measurements. We demonstrate this for a photovoltaic (PV) systems, although the methods could be similarly applied to other applications. We assess the variability in SSTDR measurements caused by changes in the PV system that are representative of normal maintenance actions such as disconnecting/reconnecting a connector and completely breaking-down/setting-up the entire system. We evaluate how this variability translates to a minimum-detectable change in impedance and how that relates to common faults in PV systems (arc and ground faults, shading, damaged cells, and aging). We also describe methods of increasing SSTDR fidelity to accurately extract minor changes in impedance and therefore, detect small-magnitude electrical faults. [ABSTRACT FROM AUTHOR]

The impact of heavy ion irradiation on the variability of 65 nm bulk Si MOSFETs is experimentally demonstrated in this brief. Due to the intrinsic random incidence of heavy ions, additional variability is introduced in the irradiated devices through displacement damage (DD) and microdose effects. For the smallest size devices, the standard deviation of threshold voltage (Vth) of irradiated devices is up to ~10% larger than fresh devices. The geometry dependence of irradiation-induced variation degradation is illustrated. The irradiation-induced variation degradation increases with decreasing gate width AND/ OR gate length, which is attributed to the irradiation-induced ionization damage fluctuation in the shallow trench isolation (STI) and spacer, respectively. The Pelgrom plot is used to quantify the irradiation-induced variation degradation. After irradiation, the slopes of fitting lines in Pelgrom plots of nMOS and pMOS devices are 10.3% and 5.7% larger, respectively. The results highlight the heavy-ion-induced variation degradation in the nanoscale CMOS devices, which bring new concerns on the design of integrated circuit (IC) for aerospace applications. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memory (ReRAM) is a promising novel memory technology for non-volatile storing, with low-power operation and ultra-high area density. However, ReRAM memories still face issues through commercialization, mainly owing to the fact that the high fabrication variations and the stochastic switching of the manufactured ReRAM devices cause high Bit Error Rate (BER). Given that ReRAM devices are nonlinear elements, the nonlinear phenomenon of Stochastic Resonance (SR), which defines that an input disturbance with specific characteristics can improve the total performance of the nonlinear system, is used to reduce the ReRAM cell’s BER. Thus, in this brief, the BER of a single ReRAM cell is explored, using the Stanford PKU model, and is improved after the application of specific additive input noise. The power dissipation of the proposed approach is also evaluated and compared with the consideration of higher amplitude writing pulses in the lack of noise, showing that the proposed noise-induced technique can decrease the BER without the excessive increase of the power dissipation. As a first step, towards the experimental verification of the proposed method, noise-induced measurements on a single fabricated ReRAM device are also performed. Overall, the presented results of the BER reduction with low power dissipation, reaching up to 3.26 × less power consumption considering 100 ns writing pulses, are encouraging for ReRAM designers, delivering a circuit-level solution against the device-level problem. [ABSTRACT FROM AUTHOR]

This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm Wfin regime, cannot be improved just by Wfin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the Wfin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

In the absence of sufficient degradation data of long-lifetime and highly reliable products, a step-stress accelerated degradation model based on nonlinear diffusion process is proposed to estimate the remaining useful life (RUL), with the advantage of requiring small sample size and short test time. For multiple uncertainties caused by inherent properties, individual differences, measurement equipment performance and artificial deviations in the degradation process, this model considers the temporal variability, unit-to-unit variability and measurement errors in both performance degradation and covariates. To estimate the RUL, we derive an analytical approximation to the first hitting time (FHT) of the nonlinear diffusion process crossing a predetermined threshold with the consideration of measurement errors. Based on maximum likelihood estimation (MLE), a modified simulation and extrapolation (SIMEX) method, called MLE-SIMEX, is developed for estimating unknown parameters in the established model. The usefulness of the proposed model is demonstrated by a simulation case and a real-world example. The results reveal that considering nonlinearity and multiple sources of variability in the step-stress accelerated degradation process can improve the model fitting and the accuracy of RUL estimation.

This investigation examines the physical mechanisms that can increase the variability of both p-n junctions and silicon–germanium heterojunction bipolar transistors (SiGe HBTs) at cryogenic temperatures. The important operative mechanisms responsible for device parameter variability include bandgap narrowing due to heavy doping, mechanical stress, and the Ge profile. The impact of direct tunneling on cryogenic parameter variability in SiGe HBTs is also examined. Measurement results are compared with TCAD simulations to provide additional insights, and possible mitigation methods are discussed. [ABSTRACT FROM AUTHOR]

In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by 4.0 × (2.7 ×) and 1.8 × (2.1 ×) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs. [ABSTRACT FROM AUTHOR]

Non-invasive continuous alcohol (ethanol) monitoring has potential applications in both population research and in clinical management of acute alcohol intoxication or chronic alcoholism. Current wearable monitors based on transdermal alcohol content (TAC) sensing have limited accessibility and blood alcohol content (BAC) quantification accuracy. Here we describe the development of a self-contained discreet wearable transdermal alcohol (TAC) sensor in the form of a wristband or armband. This sensor can detect vapor-phase alcohol in perspiration from 0.09 ppm (equivalent to 0.09 mg/dL sweat alcohol concentration at 25 °C under Henry’s Law equilibrium) to over 500 ppm at one-minute time resolution. Additionally, a digital sensor was employed to monitor the temperature and humidity levels inside the sensing chamber. Two male human subjects were recruited to conduct studies with alcohol consumption using calibrated prototype TAC sensors to validate the performance. Our preliminary data demonstrated that, under well-controlled conditions, this sensor can acquire TAC curves at low doses (1–2 standard drinks). Moreover, TAC data for different doses can be easily distinguished. However, substantial interpersonal and intrapersonal variabilities in measurement data were also observed in experiments with less controlled conditions. Our observations suggest that perspiration rate might be an important contributing factor to these variabilities. Further studies with sufficient sample sizes are required to validate and characterize the impact of different perspiration rates on TAC sensors, which may inform more reproducible and accurate sensor designs in the future. [ABSTRACT FROM AUTHOR]

Device-to-device variability of CoFeB/MgO based STT-MRAMs is studied based on experiments and simulations taking into account the influence of interface quality, temperature variation and device dimensionality. Metal-induced gap states resulting from electron transfer at the ferromagnet-tunnel barrier interface significantly influence the effective energy barrier height of these devices irrespective of their diameters. Switching voltage and parallel - antiparallel resistance values vary by as much as 43% and 30% respectively for about 13% variation of the energy barrier, whereas the tunneling magnetoresistance remains typically unaffected. WRITE cycles of highly scaled STT-MRAMs are therefore more susceptible to device-to-device variations resulting from microscopic variations in the interface quality, rather than the READ cycles. Such variations are observed to be independent of temperature, as well as spatial distribution of the defects. [ABSTRACT FROM AUTHOR]

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor (γ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that γ variability follows Pelgrom’s rule. [ABSTRACT FROM AUTHOR]

A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or drift of atomic, molecular, and/or ionic species. The average of multiple stochastic simulations is used to qualitatively explain the measured BTI and SILC data. The difference in BTI and SILC time kinetics, variation in SILC time kinetics across reports, and oxide thickness dependence of TDDB Weibull slope variation are also qualitatively explained. [ABSTRACT FROM AUTHOR]

In this study, a consistent analytical charge-based model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-number-fluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture. [ABSTRACT FROM AUTHOR]

Retinal prostheses use periodic repetition of electrical stimuli to form artificial vision. To enhance the reliability of evoked visual percepts, repeating stimuli need to evoke consistent spiking activity in individual retinal ganglion cells (RGCs). However, it is not well known whether outer retinal degeneration alters the consistency of RGC responses. Hence, here we systematically investigated the trial-to-trial variability in network-mediated responses as a function of the degeneration level. We patch-clamp recorded spikes in ON and OFF types of alpha RGCs from r d10 mice at four different postnatal days (P15, P19, P31, and P60), representing distinct stages of degeneration. To assess the consistency of responses, we analyzed variances in spike count and timing across repeats of the same stimulus delivered multiple times. We found the trial-to-trial variability of network-mediated responses increased considerably as the disease progressed. Compared to responses taken before degeneration onset, those of degenerate retinas showed up to ~70% higher variability (Fano Factor) in spike counts (p < 0.001) and ~95% lower correlation level in spike timing (p < 0.001). These results indicate consistency weakens significantly in electrically-evoked network-mediated responses and therefore raise concerns about the ability of microelectronic retinal implants to elicit consistent visual percepts at advanced stages of retinal degeneration. [ABSTRACT FROM AUTHOR]

In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and “atomistic” TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps’ different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology. [ABSTRACT FROM AUTHOR]

Silicon offers an attractive material platform for hardware realization of quantum computing. In this study, a microscopic stochastic simulation method is developed to model the effect of random interface charge traps in silicon metal-oxide-semiconductor (MOS) quantum gates. The statistical results show that by using a fast two-qubit gate in isotopically purified silicon, the two-qubit silicon-based quantum gates have the fidelity >98% with a probability of 75% for the state-of-the-art MOS interface quality. By using a composite gate pulse, the fidelity can be further improved to >99.5% with the 75% probability. The variations between the quantum gate devices, however, are largely due to the small number of traps per device. The results highlight the importance of variability consideration due to random charge traps and potential to improve fidelity in silicon-based quantum computing. [ABSTRACT FROM AUTHOR]

Resource sharing and mass storage in server farms provided by cloud platforms save huge amounts of energy. However, optimizing energy consumption at the server room is not enough, being desirable to perform energy optimization of cloud services at the application level. In cloud computing a tailored configuration of services is deployed for each client (tenant), requiring different energy consumption optimizations. Indeed, energy consumption of cloud services depends on several factors determined by the context and usage of the applications. So, to evolve a cloud application to new requirements of energy efficiency implies to perform custom-made adaptations for each tenant. Thus, managing the evolution of a multi-tenant application with hundreds of tenants and thousands of different valid architectural configurations can become intractable if performed manually. This paper proposes a product line architecture approach that: (1) uses cardinality-based variability models to model each tenant as a clonable feature, and (2) automatizes the process of evolving the multi-tenant application architecture when the energy requirements change. The implemented process is efficient for a high number of tenants in a reasonable time. [ABSTRACT FROM AUTHOR]

Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable nonvolatile memory technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<±1 V) at fast time-scales (≍10–100 ns) that make them an attractive option for not only off-chip data storage but also for on-chip embedded memory applications. ReRAM devices have also been explored for applications as reconfigurable switches in field programmable gate arrays (FPGAs). The random variabilities in the switching performance of ReRAM has been exploited to design Physically Unclonable Function (PUF) for hardware authentication, trust, and security. However, intrinsic vulnerabilities in ReRAM devices and its implications are not well-understood. Therefore, there is an urgent need to understand these so that the ReRAM-based circuits can be made robust against such attacks. This paper discusses our research on understanding the vulnerabilities in ReRAM through experimental studies and its implications on ReRAM based PUF operations. The Process, Voltage, Temperature (PVT) variabilities in ReRAM is experimentally studied and modeled. Some other ReRAM specific vulnerabilities, such as insertion of parasitic capacitances and Trojans by adversaries and its impact on ReRAM switching behavior is discussed. Based on experimental studies, models are created to capture these behaviors in ReRAM. Using these models, a 1 KB array of ReRAM devices in a crossbar architecture and its behavior is simulated. The challenge–response pairs of these ReRAM-based arrays were studied under ideal Trojan free conditions as well as with vulnerabilities models of ReRAM. Potential solutions are then proposed to make the PUF architecture and ReRAM devices more resistant to these vulnerabilities. [ABSTRACT FROM AUTHOR]

Understanding the use of haptic assistance to facilitate motor learning is a critical issue, especially in the context of tasks requiring control of motor variability. However, the question of how haptic assistance should be designed in tasks with redundancy, where multiple solutions are available, is currently unknown. Here we examined the effect of haptic assistance that either allowed or restricted the use of redundant solutions on the learning of a bimanual steering task. 60 college-aged participants practiced steering a single cursor placed in between their hands along a smooth W-shaped track of a certain width as quickly as possible. Haptic assistance was either applied at (i) the ‘task’ level using a force channel that only constrained the cursor to the track, allowing for the use of different hand trajectories, or (ii) the ‘individual effector’ level using a force channel that constrained each hand to a specific trajectory. In addition, we also examined the effect of simply ‘fading’ assistance in a linear fashion– i.e., decreasing force gains with practice to reduce dependence on haptic assistance. Results showed all groups improved with practice - however, groups with haptic assistance at the individual effector level performed worse than those at the task level. Besides, we did not find sufficient evidence for the benefits of linearly fading assistance in our task. Overall, the results suggest that haptic assistance is not effective for motor learning when it restricts the use of redundant solutions. [ABSTRACT FROM AUTHOR]

We present a predictive model for line-to-line dielectric reliability that takes variability into account. The lifetime distribution is obtained by performing series-parallel reliability computations, starting from the failure distributions of single dielectric unit cells, assumed to be Weibull. The electric field in between the lines is estimated point-by-point, and the power law is applied to account for the related impact on the Weibull scale parameter of every single cell. Finally, the model is calibrated to actual reliability measurements to fix the reference parameters of the Weibull distribution and power law. We employ our model to predict the impact of line-edge roughness (LER), and die-to-die spacing variations on the reliability of scaled interconnects and derive specs from meeting ten years lifetime at operating conditions. We show that specs can be expressed in terms of a single combined-metric, that is, the line-spacing roughness over the wafer (WLSR). Consequently, tradeoffs can be made between specs on LER and die-to-die spacing variations to achieve the same reliability margin. We calibrate our model to Time-Dependent Dielectric Breakdown (TDDB) data from low-k planar capacitors (p-caps) and generate WLSR specs for dimensions ranging from 16- to 8-nm spacing. We predict a significant drop in the reliability margin when scaling down the spacing or the dielectric k-value. As an example, we observe more than 50% reduction in the allowed σWLSR from 16- to 10-nm spacing. We also compare single with multipatterned interconnects. For spacer-assisted multipatterning, spacing edges are cross-correlated, and we predict that for the same die-to-die spacing variations more than two times higher LER is allowed with respect to single patterning to meet the same reliability requirements. [ABSTRACT FROM AUTHOR]

In this article and in its Part I, we investigate variability effects on the threshold voltage of nanowire (NW) and Macaroni devices, focusing on random dopant fluctuations and random telegraph noise (RTN) and assessing their dependencies on device radius, channel length, and doping. In this article, we address variability induced by RTN, showing that the slope of the exponential distribution follows different dependencies with respect to planar devices. We highlight the strong sensitivity of the Macaroni devices to traps at the filler-oxide interface, discussing the dependence. Finally, accumulation-mode devices are addressed, showing that they allow to achieve a lower RTN in NWs but a worse one in the Macaroni devices. [ABSTRACT FROM AUTHOR]

In this article, the dynamic variability induced by hot carrier degradation (HCD) in FinFETs is studied with decomposing the variation contributions of multiple types of traps. The nonlinear relationship of μ-σ2 (Δ Vth) are newly observed in both n- and p-type FinFETs. A multitrap-based HCD variation model is proposed and verified in FinFETs. The impacts of HCD variations on the static random-access memory (SRAM) read/write stability are also demonstrated with the circuit simulation. The results are beneficial for the reliability-aware circuit design against HCD variability particularly for FinFET-based circuits. [ABSTRACT FROM AUTHOR]

Thanks to their superior transport properties, indium gallium arsenide (InGaAs) metal–oxide–semiconductor field-effect transistors (MOSFETs) constitute an alternative to conventional silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we: 1) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs dual-gate ultrathin body (DG-UTB) FETs and 2) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against multi-subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultrathin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This, in turn, implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization. [ABSTRACT FROM AUTHOR]

In this article and the related Part II, we investigate variability effects on the threshold voltage of nanowire and Macaroni MOSFETs, focusing on random dopant fluctuations (RDFs) and random telegraph noise, to assess their dependences on device radius, channel length, and doping. In Part I, we address threshold voltage fluctuations induced by RDF and show that different trends emerge with respect to planar devices, being dependent on whether the conduction is bulk- or surface-dominated. Macaroni devices with thin silicon regions can improve RDF, while moving from inversion- to accumulation-mode devices results in a worsening of this parameter. [ABSTRACT FROM AUTHOR]

This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals. [ABSTRACT FROM AUTHOR]

This paper presents a data-driven distribution system load modeling methodology targeting quasi-static time-series (QSTS) simulation. The proposed methodology is appropriate for modeling down to the level of the customer transformer, and it has three main features: 1) both load pattern diversity and intra-second load variability are considered, 2) the load profiles can be populated for multiple nodes on a circuit in such a way that the diversity factor of the feeder can be defined and tuned, and 3) the load aggregation method can be used to populate the profiles for different nodes at various load aggregation levels. As the foundation of the modeling methodology, variability and diversity libraries have been established based on high-resolution load data collected on customer transformers from real utility feeders. The proposed modeling methodology has been used to build load data sets for both the IEEE 123-bus feeder model and a realistic utility feeder model. The QSTS simulation results on the two evaluation feeders have demonstrated that the load data sets established from the proposed modeling methodology can effectively capture the load impact on feeder operations. For the realistic utility feeder, the effectiveness of the proposed methodology has also been validated by comparing the voltage characteristics of the feeder with modeled loads and the voltage characteristics of realistic voltage data from the same feeder. [ABSTRACT FROM AUTHOR]