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Excellent open circuit voltage $(V_{oc})$ reported by Si Heterojunction (Si-HJ) solar cells has been a topic of considerable interest among the PV community. One of the reasons attributed to this large $V_{oc}$ is the reduction of interface recombination due to the presence of an inversion layer at a-Si:H/cSi interface. Here, we employ deep level transient spectroscopy (DLTS) measurements of silicon heterojunction cells (Si-HJ) to probe process induced interface traps at the a-Si:H/cSi interface. Interestingly, contrary to literature reports, we find both majority and minority peaks in differently processed Si-HJ solar cells - a result which could have interesting implications towards performance optimization.

In this work, a novel multiplexer is outlined utilizing dual gate MOSFET. This work has been completed utilizing comparable circuit of the DGMOSFET. PSPICE Simulation has been done for acquiring the reaction for the boost to the DGMOSFET based multiplexer outline. The most extreme deplete current got is 80 mA at an entryway source voltage of 5V and the variety of the deplete current as for deplete voltage is additionally gotten. 2×1 and 4×1 multiplexer configuration has been done and acquired the reaction for the jolts connected. The reenactment results are in well concurrence with the usefulness of the average multiplexer truth tables.

Most of the AC-DC systems include an AC DC converter for power factor correction followed by an isolated DC-DC converter. AC-DC converters will introduce harmonics to the input current waveform as it contains nonlinear elements, so a suitable control technique is required to smoothen the input current to reduce harmonics. For high power applications, Bridgeless interleaved (BLIL) AC-DC converter is a preferred choice. In this paper, a comparison of different control techniques that can be used for power factor correction is presented. The comparison is done with THD of supply current, supply distortion factor and supply power factor. Simulation of a BLIL converter is carried out in MATLAB/SIMULINK environment using various control techniques and the results are presented.

This research paper proposes a hybrid combination of semi-fragile Singular Value Decomposition (SVD) accompanied by Binocular Notification Difference (BND) for stereoscopic image watermarking pattern. The proposed model originated with two basic segments. At initial stage the logical intrinsic algebraic properties is used to generate content dependent watermarking through Mersenne Twister Algorithm. Once the generation of watermarking content, the BND scheme is directing the watermark embedding process. The BND inherits the tradeoff between total watermark content with clarity on visual acuity. The anticipated approach enriched through dual authentication method by chaotic map method to ensure credibility on security. Consequently the projected hybrid model is equated with other models in experimental results and analysis. This model is ensures the optimal performance against other methods in terms of tamper detection with authentication.

In this research article the digital video watermarking technique is projected through a semi-blind pattern. The proposed method involves frame-spot matching model based on KAZE method at the initial stage, The KAZE method is deployed for matching the edge points of frame-spots with all video frames with the intention to detect the embedding and extract the respective regions. Then the frame entropy blocks are designated and converted by PCA (Principal Component Analysis) blocks. The QIM (Quantization Index Modulation) is employed to quantize the highest coefficient values on each PCA entropy chunks of every sub-band. The single shared secure key is employed to recover the watermarked content. The DWT (Discrete Wavelet Transform) is applied on every single video frame and disintegrate into group of sub-bands. During extraction this is simply reversed; however the KAZE frame-spot is harmonized through each frame edge points. The parameters like rotation, scaling and translation are assessed and the watermarked evidence can be effectively extracted. The proposed pattern is verified using a numerous of video structures and compared with other similar models such as SURF, SIFT, PCA-SIFT, KAZE and perceived high optimal results. The investigational outcomes demonstrated high imperceptibility and high strength against numerous outbreaks like JPEG encoding, addition of Gaussian noise, gamma modification, histogram equality and contrast rectification in both forms of ordinary videos and clinical videos.

It is well known that the performance of Heterojunction with Intrinsic Thin Layer (HIT) solar cells depends critically on the quality of hetero-interfaces between the bulk crystalline silicon (c-Si) and intrinsic hydrogenated amorphous silicon (a-Si:H). There has been evolutionary improvement in the open circuit voltage (Voc) of HIT cells over the years primarily due to the improvements in the life time of carriers lost due to recombination at the interfaces. In this work, we present modulated electroluminescence as an alternative technique to determine the effective lifetime of carriers in HIT solar cells.

This paper enumerates the efficient design and analysis of Parallel in serial out (PISO) shift register using N-type CNTFET Double Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the dcnt of Inm in resistive load inverter logic. The transient and power analysis are obtained with operating voltage at 0.6V for the Double edge triggered D flip-flop and PISO shift register using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Considering the carbon nano tube have promising application in the field of electronics. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.

This paper enumerates the efficient design and analysis of Serial in serial out (SISO) shift register using N-type CNTFET Double Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the dcnt of 1nm in resistive load inverter logic. The transient and power analysis are obtained with operating voltage at 0.6V for the Double edge triggered D flip-flop and SISO shift register using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Considering the carbon nano tube have promising application in the field of electronics. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.

In this paper, a comparative analysis of MODFET and MESFET amplifiers was carried out. The equivalent circuit model is used for the MESFET amplifier, whereas device simulation model is used for the MODFET amplifier and the gain of the amplifiers was analyzed. In this device simulation 50 ohm resistance is used at the terminations and W = 200um, L=0.25um as device dimensions with Vds =15v and Vgs = −3v. In this paper the work is carried out using PSPICE AD simulation software.

In this paper the characterization of carbon nano tube transistor was done with c-c bond length of 0.144nm and a tube lenth o f 10nm. The work function difference of cntfet used is 0.14ev and at an ambient temperature of 300k and 77k, the chirality values of the device as n=10, m=10 and n=17 and m=17 for both the temperatures. The simulation is carried out in real space approach methodology and the results obtained are in greater coherence with the theoretical observations.

The paper presents reduced Stilted molecule that is possible for a sufficient network connection. In this paper we have reduce the stimulant for a stilted particle which forms as the basic form of the networking circuit. As the network connection some label that is referred in the previous design contains more stimulus which complicates the connection and even some part of the signal is not used for prescribed set of transfers. The newly reduced stilted molecule is designed for a specified task which often carried out by the any network layer. We have used a state method to exhibit functional ability of our design. Further a connection is establish between two device is also stimulated using Xlinx tool and model simulator. Here we are forced to answer for a question which doubts about the adaptability and extendibility of the circuit. We offer an answer that a multileveled stilted may used for the enrichment of network connection. The preference may be given based on the data, mode and devices to be connected The purpose of this chapter is to evoke the idea of living organism in a simplified terms.

Carbon Nanotube Field Effect Transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance property is determined by the so-called chirality of the tube; chirality is difficult to control during manufacturing. This results in conducting (metallic) nanotubes and defective CNTFETs similar to stuck-on (SON or source-drain short)faults, as encountered in classical MOS devices. This paper studies this phenomenon by using layout information and presents modeling. For CNTFET-based circuits (e.g. intramolecular), these defects are analyzed using a traditional stuck-at fault model. This analysis is applicable to primitive and complex gates. In this paper, we have also developed a simple analytical model for ballistic nano transistors that operate by modulating the charge in the device (as opposed to modulating the current at the contact). This analytical model captures the essential physics of MOSFET-like ballistic[10] nanotransistors and provides a convenient way to assess and compare transistors at the ballistic limit. The circuit simulation was carried out using SPICE model and the current voltage characteristics were obtained.

This paper presents the practical and theoretical design of the power supply unit (PSU) of the Sathyabama University Nano Satellite. The solar arrays are configured such that the cells of each side on the satellite are connected in series and the four sides are connected in parallel. This configuration has been chosen, because it was found that it is the best trade off between ease of maximum power point tracking(MPPT) and to improve the converter performance. The diodes protect the cells from conducting a reverse current. The battery charge controller acts as a central unit of the electronic subsystem, it takes care of charging the battery unit. It basically transfers power from solar panel to the battery at unregulated bus. The choice of battery configuration and capacity is calculated on the basis of orbital calculation. This battery is also responsible for voltage control of the intermediate power bus between the two converters. The batteries keep the average voltage in the range 6.0–8.4V. This is used to convert the intermediate bus voltage to 5v and 3.3v bus levels for the other subsystem. The simulation results of various converters are shown.

In this paper, we have proposed the compact modeling of ballistic CNTFET and the performance analysis of the developed model using various characteristics. The carbon nanotube transistors (CNTFET) are currently considered and most promising component to replace the generation of MOSFET transistor, especially in order to surpass the short channel effects in the component. For this new generation of transistor (CNTFET) with very short channel, the majority of models describing electrical conduction based on the process of ballistic transport. We propose design-oriented compact models for ballistic CNTFET. We are interested more particularly to the drain current and the quantum capacitance as a function of the gate voltage (VGS), for various values of the nanotube diameter and the oxide thickness. These models have been simulated and the results that are obtained were in excellent agreement with the theoretical calculations.

Time - dependent characteristic of buried-gate GaAs MESFET with front illumination have been analyzed by solving continuity equation. This analysis includes the ion implanted buried-gate process. At time ‘t’ is equal to zero, the light through the optical fiber is turning ‘ON’ and ‘OFF’ has been considered. The channel charge and channel current have been evaluated and discussed. Buried-gate optical field effect transistor (OPFET) will be highly suitable for optical communication and optical computing.

This paper provides new insight into the cause of photovotage generation and channel conductance variation in an ion-implanted buried-gate GaAs MESFET with front side illumination. When optical fiber with modulated frequency falls on the device, flow of charge carriers changes corresponding to the change in the wavelength and frequency of incident light. The photo voltage is developed due to the transport of holes across the schottky junction .The data suggest that the magnitude of photo voltage increases, and as a result, there are more uncovered ionic charges in the space charge region toward the drain-side of the gate. This analysis including surface states and the ion implanted buried-gate process. The access charge density at the drain-side of the depletion induces opposite charges in the gate electrode. Consequently, it gives forward biasing to the Schottky barrier gate which increases with increasing values of Ids. As a result, the modulation of channel conductance and photo-voltage characteristics due to the buried-gate GaAs MESFET becomes high effective. The results indicate very good performance of the device compared to other devices like MESFET under back illumination and MESFET with front illumination having surface gate.

In this paper, an analysis on the effect of noise on the performance of the MODFET was carried out. Here the MODFET model considered is of 0.25 × 200 um2 technology. The equivalent noise model is used and the transconductance with respect to frequency is analyzed and also the variation of the drain current with frequency is also analyzed under the influence of the noise. In this paper the work is carried out using PSPICE AD simulation software.

DC characteristics of buried-gate GaAs MESFETs are studied by solvifg dc coftifuity equatiof. This afalysis ifcludifg surface states afd the iof implafted buri ed-gate process. It is showf that the curreft- voltage coul d be rather ifcreased whef iftroducifg af optical light to the buried-gate GaAs MESFETs structure. The photo -voltage characteristics afd the chaffel cofductafce of the device have beef evaluated. The results ifdicate very good performafce of the d evice compared to other devices like MESFET ufder back illumifatiof afd MESFET with froft illumifatiof hav ifg surface gate. Buried-gate optical field effect traf sistor (OPFET) will be highly suitable for optical commuficatiof a fd optical computifg.

Addition of different service requirements by users and advent of new access networks have increased the complexity to manage these networks uniformly. However, there are many management protocols available today like SNMP, JMX, WBEM, etc, which are being used to manage networks. Because of complexity and heterogeneity of these management protocols it has become very difficult for a network manager to manage different network elements (NE) since these may be instrumented using different such protocols. One critical example of such a complex network is IP Multimedia Subsystem (IMS). 3GPP does not specify the management protocol to be used to manage network elements in IMS. In this paper, the authors have proposed a novel network management solution, which can be used to manage IMS components independent of heterogeneous management protocols like WBEM, SNMP, JMX etc. Moreover, authors have developed a prototype resource adapter to test the suitability of the protocol.

Using a 60 cc spherical graphite ionization chamber as the Primary Standard the HDR Ir-192 source was standardized at the hospital site in a minimum scatter geometry, in units of Air Kerma Strength (AKS). A 400 cc bakelite reference chamber was calibrated against the Primary Standard. It was seen that the Primary Standard and the Reference chamber, both being of low Z, showed roughly the same scatter response and yielded the same calibration factor for the 400 cc reference chamber, with or without scatter. The scatter correction, however, is required for the determination of the Air kerma strength. The theoretical Monte Carlo estimates of the scatter corrections, obtained by simulating the source and the room geometry, showed excellent agreement with the experimental values. This reference chamber can now be used at other hospital sites for determining the AKS of the source, by applying proper scatter corrections. However, any likelihood of change in the reference chamber calibration would necessitate the transport of the Primary Standard to the hospital site for recalibration. Frequent transport of the Primary Standard can lead to changes in its response due to movement or other extraneous causes. The calibration of the Reference chamber against the Primary Standard at the Standards Lab., for an industrial type Ir-192 source maintained at the lab., showed excellent agreement with the hospital calibration, making it possible to check the reference chamber calibration at the lab. itself. Further work is in progress.