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Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as $0.3\times $ VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates. [ABSTRACT FROM AUTHOR]

This article presents a universal modular hybrid low-dropout regulator (MHLDO) to provide any desired combination of the power supply rejection ratio (PSRR) and power conversion efficiency (PCE) with in-compliance output ripple, load transient response, and operating range while minimizing losses and decoupling capacitor. The hybrid architecture eliminates the need for the fine quantization of the digital LDO power gates and prevents any associated limit cycle oscillation while keeping the overheads low. It is configurable at design-time and robustly self-adjusts across different operating points via a scalable architecture. The modular topology overcomes significant challenges of developing a large variety of analog and digital LDOs in order to meet the varying PSRR and power budget requirements for systems on a chip (SoCs) in scaled CMOS. A nonlinear control (NLC) feature provides an energy-efficient way to respond to fast load transients, while the dynamic clamp strength tuning (DCST) technique prevents unnecessary oscillations stemming from the input parasitic inductances and improves stability while lowering switching losses. The designed MHLDO provides a programmable PSRR capability of up to −42 dB with a quiescent current of less than 27.3 $\mu \text{A}$ as ALDO and a 133-mV worst droop against a >1-A/ns fast di/dt load change as DLDO. A new figure of merit (FoM) with improved accuracy demonstrates performance of 83 fs. [ABSTRACT FROM AUTHOR]

Distributed charge injection (CI) scheme featuring distributed $V_{\mathrm {MAX}}$ -complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in a 10-nm CMOS test chip. A local DDD detects nearby voltage droop and quickly triggers associated CI clamps to inject charge from an additional high-voltage rail (e.g., 1.8 V) to $V_{\mathrm {CC}}$ for immediate voltage droop mitigation. Distributed droop controllers collectively guarantee stable operation after CI is triggered by gradually allowing the voltage regulator to take over after the droop subsides. Detailed simulations supported by a theoretical analysis give the necessary conditions for stable distributed CI operation. At 0.8 V/1.4 GHz (1.0 V/2.0 GHz), the measured data from a 10-nm test chip show droop reduction by up to 74% (45%) for a uniform transition and by 56% (38%) for a hot-spot transition. The droop reduction is translated to power savings of ~11% over a guard-banded baseline. [ABSTRACT FROM AUTHOR]

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail. [ABSTRACT FROM AUTHOR]

Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The challenges of implementing efficient discontinuous conduction mode (DCM) operation at high switching frequencies are discussed, which include zero current detection, inductor ac-loss effects, and power delivery network (PDN) resonances. A prototype in 14-nm CMOS is presented, which shows the DCM operation at up to 70 MHz with a peak efficiency of 88% for 1.6–1.2-V conversion. [ABSTRACT FROM AUTHOR]

A fully integrated digitally controlled buck voltage regulator, featuring hysteretic and pulse frequency modulation control for maximum light load efficiency, with 3-D through-silicon-via-based on-die solenoid inductor with a planar magnetic core in 14-nm tri-gate CMOS, demonstrates 111 nH/mm2 inductance density and 80% conversion efficiency. The inductance density demonstrated is 20 $\times $ higher than comparable on-die lateral- or spiral-based inductor densities leading to higher light load efficiency. [ABSTRACT FROM AUTHOR]

A fully integrated digitally controlled two-phase buck voltage regulator (VR) with on-die solenoid inductors with a planar magnetic core is demonstrated in 14-nm tri-gate CMOS for fine-grained power delivery/management domains of high power density in system-on-chips while enabling ultra-thin (z-height) packages. The VR achieves 1-A/mm2 power density for 400-mA load current with a measured peak efficiency of 84% at 100-MHz switching frequency including a digital PWM with >9 bits (8 ps) of resolution. [ABSTRACT FROM AUTHOR]

An energy-harvesting wireless sensor node (WSN) integrates a 14-nm, 0.79-mm2, 32-b Intel Architecture core-based near-threshold voltage (NTV) microcontroller (MCU) that provides 17- \mu \textW /MHz always-ON, always-sensing (AOAS) capability. The MCU implements four independent voltage-frequency islands, managed by an integrated power management unit and features a subthreshold voltage capable on-die oscillator and 42-nm fin-pitch, 8.3-pA leakage-per-bit SRAM. The MCU operates across a wide frequency (voltage) range from 297 MHz (1 V) to 0.5 MHz (308 mV), dissipating 23.5 mW to 21 \mu \textW , and achieves $4.8\times $ better energy efficiency at an optimum supply voltage ( V_{\text {OPT}} ) of 370 mV, 3.5 MHz, and 17 pJ/cycle. A functional AOAS WSN incorporating the NTV MCU shows promise for sustained \mu \textW operation. [ABSTRACT FROM AUTHOR]

In high volume manufacturing, conventional approach to deal with inverse-temperature dependence (ITD) and aging is to add a postsilicon flat voltage guard band to all dies based on testing a small random sample of dies. Although this scheme guarantees error-free operation, it significantly degrades energy efficiency, as it penalize all dies for the maximum delay degradation due to ITD and aging as seen by the worst case die, while also assuming maximum aging condition. In this paper, a graphics execution core implemented in 22 nm trigate process uses per-die tunable replica circuit (TRC) to monitor delay degradation due to ITD and actual aging conditions. TRC triggers adaptive voltage scaling to dynamically adjust V\mathrm {CC} as needed during run time to maintain correct operation at minimum additional voltage. Measured data show up to 33% (14%) energy savings at 0.4 V (0.8 V) compared with baseline scheme. The TRC is also utilized in a dynamic power gating (DPG) scheme to lower energy overhead due to fast droop guard band. DPG introduces a load line effect during normal operation, thus saving energy, while deactivating this load line upon droop detection by the TRC to maintain ISO performance as baseline. Silicon data show that DPG can improve energy efficiency by 14.5% (7%) at 0.8 V (0.6 V). [ABSTRACT FROM AUTHOR]

This paper presents an adaptive and resilient domino register file design featuring in-situ timing margin and error detection for the performance-critical domino read path. Voltage/frequency is adapted for slow-changing variations such as low-frequency supply noise, temperature fluctuation, and aging-induced degradation. Dynamic adaptation is combined with error detection and recovery for fast voltage droops and random data access patterns in the presence of within-die process variations. Throughput and energy efficiency gains are higher than the replica/canary based critical path approach. Timing margin is tracked by double-sampling the read output and its delayed version at the same clock edge. Timing errors are detected by double-sampling and comparing the read output within a clock window. The sensing errors in the precharge/evaluate domino read path are converted into timing errors using a conditional delayed-bitline precharge technique that does not impact the subsequent precharge operation. The proposed techniques incur 6–13% area overhead and 0.2–0.3% power overhead for a 4 Kb sub-array. The measurement results from a 22 nm tri-gate CMOS testchip demonstrate 21% throughput and 67% energy efficiency improvement with a peak energy efficiency of 409 GOPS/W. [ABSTRACT FROM PUBLISHER]

A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows \sim75% core frequency improvement at 0.84 V. [ABSTRACT FROM PUBLISHER]

Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of < 50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements. [ABSTRACT FROM PUBLISHER]

The need for fine-grained power management in digital ICs has led to the design and implementation of compact, scalable low-drop out regulators (LDOs) embedded deep within logic blocks. While analog LDOs have traditionally been used in digital ICs, the need for digitally implementable LDOs embedded in digital functional units for ultrafine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control model of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current efficiency of 98%. [ABSTRACT FROM AUTHOR]

A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45–1 V from a fixed input voltage of 1.225 V. It achieves 63–84% conversion efficiency and supports a maximum load current density of 0.88 A/mm 2 . The area overhead of the dedicated SCVR on the load is 3.6%. Measured data is presented on various performance indices in detail. Subsequent learning on tradeoffs between various factors like capacitance characteristics, conversion efficiency and current density are delineated and, correlated with theoretical estimates. Performance of RF array shows comparable results when powered with the SCVR and the external rail. The all-digital, modular design allows efficient spatial distribution across the load and hence robust power delivery. The extremely fast response times in the order of few nanoseconds is targeted to benefit agile power management. This work evinces voltage regulator technology as a standard homogenous CMOS component, which can proliferate DVFS domains for maximum energy and area benefits. [ABSTRACT FROM PUBLISHER]

Advanced human-machine interfaces require improved embedded sensors that can seamlessly interact with the user. Voice-based communication has emerged as a promising interface for next generation mobile, automotive and hands-free devices. Presented here is such an audio front-end with Voice Activity Detection (VAD) hardware targeted for low-power embedded SoCs, featuring a 512 pt FFT, programmable filters, noise floor estimator and a decision engine which has been fabricated in 32 nm CMOS. The dual-VCC, dual-frequency design allows the core datapath to scale to near-threshold voltage (NTV), where power consumption is less than 50 uW. At peak energy efficiency, the core can process audio data at 2.3 nJ/frame—a 9.4X improvement over nominal voltage conditions. [ABSTRACT FROM AUTHOR]

An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (VCC) droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a VCC droop. The tunable-length delay prevents critical-path timing-margin degradation for multiple cycles after the VCC droop occurs, thus allowing a sufficient response time for dynamic adaptation. An on-die dynamic variation monitor detects the onset of the VCC droop to proactively gate the clock at the end of the tunable-length delay to eliminate the clock edges that would otherwise degrade critical-path timing margin. In comparison to a conventional clock distribution, silicon measurements from a 22 nm test chip demonstrate simultaneous throughput gains and energy reductions of 14% and 3% at 1.0 V, 18% and 5% at 0.8 V, and 31% and 15% at 0.6 V, respectively, for a 10% VCC droop. [ABSTRACT FROM PUBLISHER]

Infrequent dynamic events like V CC droops and temperature changes result in the use of a static V CC guardband in 8T SRAM arrays. This paper proposes the use of tunable replica bits (TRBs) as a potential solution to mitigating a part of the V CC guardband. Measured data on a 16 KB 8T array featuring tunable replica bits illustrate 9% reduction of the operating minimum V CC\ (V MIN) and correspondingly a 7.5% reduction in array power. [ABSTRACT FROM AUTHOR]

A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (FCLK) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the FCLK guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (VCC) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency VCC droops. [ABSTRACT FROM AUTHOR]

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (Vcc) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal Vcc or at least 17% Vcc reduction at equal throughput, corresponding to 31 %-37 % total power reduction. [ABSTRACT FROM AUTHOR]

The article reports on the prevention of wire degradation in computer chips. Electromigration in microprocessor design can cause the wires in chips to degrade and it can be prevented through refueling in bidirectional wires. Refueling, where current is injected in one direction when the current is higher in the opposite direction, balances the current which flows in both directions of a wire and improves the life of a chip's wires. Wires can also be made wider in order to reduce the current densities passing through them.

The article discusses the impact of parameter variations of circuits and microarchitecture. Timing and power are both affected by parameter variations which are increasing along with the advances in process technologies. In the circuit and microarchitectural design levels, variability must be considered in order to keep pace with performance scaling and to keep power consumption within reasonable limits. The article also presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.

Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between them. Active shielding is another shielding technique in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This paper formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (γ = Cc/Cg). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A suboptimal active shielding architecture with simpler hardware is also proposed. Theoretically, using the suboptimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit. However, due to the simpler shield encoding circuitry, simulation results show that the suboptimal active shielding architecture leads to higher overall energy savings compared to the optimal active shielding architectures. [ABSTRACT FROM AUTHOR]

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-VT CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10× better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits. [ABSTRACT FROM AUTHOR]

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm² experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W. [ABSTRACT FROM AUTHOR]

In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 µs, resulting in 37× reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2× with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75 °C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile. [ABSTRACT FROM AUTHOR]

Investigates the effectiveness of adaptive supply voltage and frequency binning of fabricated microprocessors. Description of a test chip fabricated in complementary metal oxide semiconductor technology; Measurement of the test chip; Distributions of frequency, active power, switched capacitance and standby leakage power.