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With the development of electronic packaging technology in 5G era, System-in-Package (SiP) module is developing into smaller size and higher integration to realize the multi-functional applications, and the reliability of SiP module, especially the interfacial delamination has become one of the most concerned issues. To predict interfacial delamination precisely through modeling and simulation methodologies, accurate warpage of SiP module should be calculated accordingly since warpage deformation is one of the main reasons of interface delamination. For plastic packaged devices, like most SiP modules, coefficient of thermal expansion (CTE) mismatch between epoxy molding compound (EMC) and its adjacent materials will lead to warpage during the process of transfer molding and post-mold cure of EMC. In addition to this, another important reason of warpage is the chemical shrinkage of EMC during curing process. In this work, a method of characterizing cure shrinkage of EMC was proposed by using bi-material test method. The cure shrinkage rate of EMC was calculated combining the simulation methods and the warpage test results, which was applied in optimizing the SiP module warpage simulation during reflow process. Furthermore, the effect of viscoelasticity of EMC on SiP module warpage was also investigated in this work.

With the continuous improvement on the function of electronics, the IC integration density is gradually increased. Meanwhile, the stacked chip packaging technology appeared to meet the requirements of chip integration. Among them, the cantilever stacked chip structure not only increases the package density, but also satisfies the need of vertically integrated chips with the same size. However, the gold wire sweep induced during the transfer molding process is still one of the critical issues for the reliability of the cantilever stack structure. Therefore, it is of great significance to explore the wire offset in the process of transfer molding to enhance the reliability of stacked chip packaging. In this paper, a mold-flow analysis model of cantilevered chip-stacked structure is setup. The viscoelastic properties were measured by using a DMA analyzer. For studying the deviation of wire loop in transfer molding, the process parameters including the molding temperature, filling time and melt temperature are analyzed by finite element simulation. Firstly, the effect caused by different positions of the gate on the wire offset also is studied. Secondly, the influence of the above process parameters on the position deviation of gold wire is studied following an orthogonal experiment route. The results show that the inhomogeneous temperature field caused by transfer molding has an affect the quality of the chip wire bonding, while the melt temperature has a great influence on the wire offset. Due to the influence of the flow rate of transfer molding, the closer the wire to the gate position is, the larger the offset will be, especially for the wire perpendicular to the gate position.

Today's flip chip scale packaging (FCCSP) microelectronics products are becoming more and more complex, especially in the packaging process using molded underfill manufacturing, which reduces the cost of flip chip technology such as molded underfill (MUF) High, provides molding ability in molding. The problem is to leave effective space under the chip. Generally speaking, this requires a lot of experimental DOE (chip size, substrate design, and epoxy resin type) to solve this problem. For the reasons mentioned above, mold-flow simulation software can be applied to use different flow condition to obtain the best solution as the MUF FCCSP of the substrate structure design. Such a simulation method can help shorten the product development cycle. This article uses the commonly used 3D molding process simulation software for transferring manufacturing process parameters. This article will introduce a comparison of two different structures. A MUF is FCCSP, it is matched with different bump height (SOH) structure comparison (control the flow of different chip bottom space), and observe the difference of the flow melt-front. The second is that there are two different designs on the surface of the substrate (welding masks with completely open or partially open patterns) through the table to enter the previously separated welding mask samples (welding masks with l0um depth structure) to maintain different modes. As this research, we can get a lot of conclusion that improve the molding capability of molded underfill FCCSP in the transfer molding process. If the bottom of the molded underfill FCCSP chip is matched with a structure with a height of 55 µm, then the molding epoxy can easily flow under the area with a large flow space, so the risk of entrapment can be reduced. In addition, the molding compound also has good melt front fluidity, and the fully open substrate surface design of the substrate solder resist layer can achieve more l0µmm space underneath the die area. Then, the CAE output are consistent as the experiment and it can to predict whether the product has a risk assessment of void.

In flip chip packaging, the molded underfill (MUF) integrates the underfilling and molding processes to reduce manufacturing cost and cycle time of process, but is difficlut to obtain high quality filling due to void trapping problem. Virtually, from a technical perspective, it is a microinjection molding process, the MUF process can be thought as a pressure-driven suspension flow. For transfer molding, the main factors affecting the reliability of products include the properties of filling materials, injection process parameters and the geometry of the cavity. In this paper, 3D mold flow modeling of the transfer molding process with MUF using Moldflow is applied. By designing DOE experiments, the MUF process parameters were optimized under different packaging structures of flip chip, and the influence of different methods of chip placement on the molding results was discussed, providing a basis for the design and optimization of process parameters and chip geometry structure.

System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing parameters and processes [1], [2]. Previous research on the warpage primarily focused only on the SiP module unit, while the consideration of strip warpage as a function of manufacturing processes has not typically been studied theoretically and experimentally. In this paper, the impact of manufacturing processes, mainly the compression molding process, on the warpage is investigated experimentally and numerically. To better understand the advantages of compression molding, we will also compare compression molding with transfer molding using a computer simulation. The paper will point out the pros and cons of these two different manufacturing processes.

Silicone materials are well recognized for their excellent photo/thermal stability, owing to which they are often used as adhesives or encapsulants in electronics applications. However, silicone materials can also present a challenge due to their high Coefficient of Thermal Expansion (CTE) which can generate thermal stress because of CTE mismatching with the substrate. While a “soft” silicone compensates for CTE mismatch through deformation during thermal stress in a device setting, this mismatch limits the use of “hard” silicone products in the market (this limitation was the first market need we addressed in our study). On the other hand, readily available silicone adhesives or encapsulants are mostly curable liquid or paste forms. Organic counterparts such as epoxy or acrylic materials offer “hotmelt” products to cover specific market needs in transfer molding (cylindrical tablet) or large area encapsulation (film/sheet). While the market demand for curable silicone hotmelt products is emerging, only a few such products have been realized thus far (this unmet demand is the second market need we investigated). Our recent study on silicone hotmelt has shown that thermal stress management is feasible even with silicone compositions producing relatively “hard” cured monolith; silicone hotmelt enables an extreme ratio of the raw materials, which is impossible by typical curable liquid compositions. In this presentation, we will introduce novel silicone hotmelt solutions to meet emerging urgent technological requirements such as ease of handling, thermal stability or reliability against thermal stress. The first solution is heat curable silicone hotmelt cylindrical tablet for transfer molding. This aims to achieve similar handling/property to epoxy molding compound (EMC) tablet with superior thermal stability. Silicone hotmelt technology combined with novel compounding technology enabled extreme hardness and CTE of the cured piece; it provides a tensile modulus of 8 GPa and a CTE of as low as 11 ppm/°C, which are comparable to typical EMC. It has been confirmed that molded piece with a PCB board did not show any warpage, indicating matched CTEs in a molded body. Furthermore, the prototype showed no significant degeneration in mechanical and adhesive properties up to 1000-hour exposure to 250°C. In conjunction with optimized melt/flow performance of the prototype, this can be a novel solution for electronics encapsulant applications requiring extreme thermal stability. The second solution is heat curable silicone hotmelt film for large area encapsulation or adhesion. Large area molding is an emerging trend in electronics to achieve higher production output. Utilizing curable liquid products in this application is cumbersome because it requires dam material for precise control of the layer thickness. Furthermore, CTE mismatch between silicone and the substrate becomes a serious issue because of the relatively large thermal stress coming from the large area size. On the other hand, material providing a modulus in GPa range (such as the aforementioned cylindrical tablet material) cannot be applied to flexible devices. To meet these needs, novel silicone hotmelt film prototypes have been developed. Cured monolith from this prototype provides a tensile modulus of 10–100 MPa and a CTE of 220 ppm/°C. While the CTE is high, the designed rheological property enabled excellent stress relaxation capability to minimize the thermal stress in a molded body. No warpage has been observed when molded onto an 8-inch wafer. Controlled modulus of the cured piece bestowed flexibility and low surface tackiness at the same time. The melt/flow performance was optimized for vacuum lamination with excellent gap-filling capability. Furthermore, this prototype exhibited excellent adhesion capability to various substrates including fluoro-based materials and precious metals such as gold. Unique features realized by this silicone hotmelt film are expected to meet emerging market needs in materials for large area encapsulation or adhesion. General trends in electronics include miniaturization of devices and simplification of the production process. As devices become smaller and thinner, encapsulant or adhesive is likely to be exposed to harsher conditions, i.e. higher temperature or stronger light. In light of these trends, silicone is becoming more and more suitable, but current usage of conventional silicone products is limited because of its low modulus and product form (liquid or paste). The novel technologies described in this presentation will break some of these barriers and open a door to utilize silicone in applications where it has never been used before.

CNT/CNF grown on fabric can be later used to produce the composite plates through resin transfer molding or autoclave methods. Since the CNT/CNFs on the fabric will not cause a problem like increasing resin viscosity, they will clearly show a more homogenous distribution. By growing CNT/CNFs on fabric, it is possible to reach high ratios like 10%. However, potential problems during production of composite at high CNT/CNF ratios using such a technique remain unknown. This study examined basic mechanical properties and damage development properties of composite plates produced with CNT/CNF grown on 2×2 twill woven carbon fabric and compared the results with composite materials without carbon nanotubes. CNT/CNF grafting at high amount causes a CNT forest around the fiber and this causes significant limitations in composite material production. Due to increased distance between the fibers, local fiber volume fraction decreases within the yarns. Fiber volume fraction was found to decrease by 2.7-6.2 % according to CNT/CNF ratio. The results revealed that there were significant decreases in mechanical properties and characteristic strain values where damage initiation and progression of the composite samples produced from carbon nanotubes grown on fabrics. It was found that Young's modulus values decreased by 15-17%. Characteristic strain values where damage threshold decreased by 36-53%. It was concluded that decreased local fiber volume fraction and low fiber-matrix interface bonding were the main cause for this situation. Moreover, it is believed that the one of the most important factor that might cause these limitations is lack of adequate wetting of fiber surfaces and low fiber-matrix interface bonding.

The molded underfill (MK) process for system-in-package (SiP) assembly has been widely used for recent years. In the past, the main structure of the MK was molded flip chip chip scale package (MFCCSP). Later, as the number of components increased, the mold flow became complicated, and the void issue increased, it evolved into complicated SiP. Nowadays, the metal lid SiP module is gradually moving towards the MUF SiP package market. Transfer molding for SiP is widely used in product packaging nowadays, such as mobile watch, wifi module and power management integrated circuit (PMIC) for mobile phone and portable devices, etc. The microelectronics products of SiP with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as surface mount technology (SMT) density, component counts become larger and number of bumps increase, especially when transfer molding process is used. There is one important challenge that faced severe air void entrapment under the die (bumps region). At present, there are mainly the following reasons leading to void issues: 1. mold thickness is too thick, 2. bump counts increase or smaller bump height, 3. mold gap smaller, 4. viscosity of epoxy molding compound (EMC) is too high. Generally, the experiments involving a lot of design of experiment (DoE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP with mold thickness and mold gap design, which can reduce development cycle time before mass production. In addition, the trend of the impact on void will be discussed in the acceptable range of EMC material properties and cavity vacuum value. At present, there are several key factors that affect void issues, including component/mold volume ratio, main component size, space in end of row, side space, mold thickness and bump layout, etc. We have proposed general design guidance for low risk: mold thickness divided by minimum bump thickness index should be less than 5. If number of bumps is greater, decrease mold thickness can improve void risk issue. The results of mold flow simulation indicate that the above mentioned advanced SiP package structure design would lead to low void issue. The transfer molding mechanism and the design guidance of SiP for engineering application will be presented and discussed in this paper.

We propose a new low-inductance power module structure for double-sided cooling. In the proposed structure, DC terminals are branched, and the positive and negative terminals are alternately arranged for magnetic field canceling. By arranging these terminals on the same plane and designing them to have the same thickness, these terminals can be pressed by a transfer molding die. Our proposed structure can reduce stray inductance and be applied to transfer molding, which ensures its reliability by resin encapsulation. This paper presents the experimental results of the proposed structure. We prove that the proposed structure can reduce inductance better than the conventional type.

Components made from carbon fiber reinforced plastics (CFRP) offer attractive stability properties for the automotive or aerospace industry despite their light weight. To automate CFRP production, resin transfer molding (RTM) based on thermoset plastics is commonly applied. However, this manufacturing process has its shortcomings in quality and costs. The project CosiMo aims for a highly automated and cost-attractive manufacturing process using cheaper thermoplastic materials. In a thermoplastic RTM (T-RTM) process, the polymerization of ϵ-caprolactam to polyamide 6 is investigated using an intelligent mold tooling. Multiple sensor types integrated into the mold allow for tracking of process-relevant variables, such as material flow and polymerization state. In addition to monitoring the T-RTM process, a digital twin visualizes progress and makes predictions about issues and countermeasures based on machine learning.

At present, System in Package (SiP) is getting more and more applications in power packages. Due to the complexity of the packages, the molding process becomes crucial for the yield and reliability of the products. During the transfer molding process, the packaging processes of the packages may introduce assembly defects, such as void, wire sweep, warping, etc. To determine the main factors is one of the most important measures to eliminate and prevent these defects.In this paper, 3D Molding flow simulation for the SiP package is conducted by using the Moldflow software with the aim to predict the location of the void and weld line during the plastic package process. The influence of gate design on process-induced defects and other reliability issues was studied. The results show that the filling of different gate locations in the package will produce cavitation defects at different locations. A gate design with fewer corners in the injection direction will produce fewer cavitation. Increasing the number of gates will reduce air pockets at the corners, but will cause more air pockets near the weld line. When the gate position is perpendicular to the top surface of the chip, less weld marks are generated. The flow front will produce weld marks after being blocked. When the number of gates increases, the area of the flow front increases and the number of weld lines increases significantly.

2.5D multichip module packaging technology for higher end devices like CPU, GPU, 3D NAND flash memory and High Bandwidth Memory (HBM) require two major molding process solutions: higher thermal performance and narrow gap underfill. Apic Yamada Corporation of Japan, as a semiconductor back end total solution provider, proposes technology solutions utilizing advanced molding technologies which enable chip surface exposure and Mold Underfill (MUF) for narrow gaps.With conventional molding technology, the mold resin on the top surface of the chip is removed by a grinding process after the molding process in order to improve thermal resistance θja. However, the latest transfer molding technology enables chip exposure without a grinding process. This technology can be applied to a wide range of higher end advanced packaging technologies such as 2.5D, 3D and others. The conventional chip exposure molding method using elastic release film, which covers the inside of the mold cavity, can absorb chip height variations. In addition, the most advanced available chip exposure molding system applies reduced pressure and lower mechanical stress to the chip. This low stress molding process comprises several new system technologies including chip height measurement using a laser displacement sensor, which is self-calculating to provide the optimum cavity level for chip exposure, by adjusting the cavity block position each cycle.In this study, solutions for chip height variation such as +/- 20um and height control range within 300um with low stress will be presented. In addition, we propose newly developed vacuum molding technology and movable air vent technology for MUF with void less filling of narrow gap spaces under the chips. Proper mold resin material selection to achieve high filling, optimal heat shrinkage and minimized warpage is one of the key factors. The new technology also provides economic advantages due to reduced process steps and shorter process time compared to the Capillary Underfill (CUF) process which is widely used in the marketplace.In order to achieve a reliable MUF process targeting less than 8um gaps and less than 15um pitch, Apic Yamada’s molding system has tighter control for discharging internal air and generated gas to the outside. This is accomplished while also controlling vacuum conditions, using chip volume measurement by laser displacement sensor and 3D image measurement which calculates the resin flow front on each shot.

This paper reports a new design of a 4-pack super-junction MOSFET power module using a transfer molding process. This module initially targets industrial applications, such as photovoltaic (PV) inverters or energy storage system (ESS). Many conventional 650V power modules are gel-filled IGBT modules, but our transfer molded super-junction MOSFET power module can satisfy electrical insulation and thermal conductivity with potential reduction in production cost and module volume. Super-junction MOSFET dies are soldered on a direct bonded copper (DBC) substrate in the power module. Fabrication process is also customized to the molded super-junction MOSFET module. The designed power modules are successfully fabricated, demonstrating a volume reduction. The fabricated modules are evaluated by FEM simulations and experiments, which exhibit excellent thermal and electrical performances. A small thermal resistance (~0.26 K/W) and package on-resistance (~15.7mΩ) are achieved.

The process of microchip encapsulation by epoxy resin injection is simulated by employing moldflow modeling. In this work, the use of modeling allows to reproduce the unbalanced flow behavior of the resin within the mold cavity during the filling stage which leads to the formation of voids in the molded package. Simulation results are compared to experimental findings, in which the molding process is interrupted at designed points in time. Comparison shows good agreement between numerical outputs and experimental data and demonstrates the effectiveness of the model. After modeling is validated, the numerical methodology is applied to optimized package design in order to minimize the risk of issues caused by the filling stage. As a result, geometric variations show a significant effect on filling front progression avoiding the generation of structural defects during molding process.

Various definitions of shrinkage are reviewed: mold shrinkage, total chemical shrinkage and effective chemical shrinkage. Their relationship with the curing-induced residual stresses is discussed. Then, an advanced technique, called "dual configuration fiber Bragg grating (DC-FBG) technique", is employed to measure the effective chemical shrinkage of EMCs for two conditions: after removing the mold pressure before curing and while maintaining the pressure during curing. The results are discussed with the transfer molding and compression molding processes. A procedure to estimate the total chemical shrinkage from the mold shrinkage is also presented.

IC Package moldings are getting complex and now cater to high performance and non-standard design configurations with technology advancements. Also increasing yield requirements to reduce molding costs of transfer molded packages necessitate optimal spatial distribution of multitude package cavities within the molded lead frame strip and entail significant constraints on molding tool and process and impose challenges to moldability of such high density packages with minimal quality defects.However molding these large cavity arrays constrains tooling configuration such as reduced runner/gate geometry dimensions which largely affects mold compound flow entry into cavities through gates in all cavity rows. Flow from cull to the end rows require longer transfer time with significant variation in resin characteristics till the cavities are completely filled. Such non-uniform filling of cavities cause molding defects due to variations in balanced filling, wire-sweep, voids, uneven filler distribution and variation in adhesion of molding compound to lead surfaces in different sections of the molded strip. One such case observed is the segregated filler distribution adjacent to gate and zero-hour delamination observed in first few rows of the molded strip adjacent to gate entry into cavitiesMolding process analysis on cavity filling of such large strip packages helps to gain understanding on the flow progression stages and also inquire on dynamic flow parameters such as the resin temperature, velocity, shear rate, cure and viscosity and as well helps to deduce the variations in delamination observed in molded packages. High velocity vectors seen over die pad and leads adjacent to gate indicate resin flow jetting exerting high-velocity shear flow parallel to the leads and possible cause for inferior adhesion of the resin to the lead surfaces increasing their susceptibility to delamination at the mold compound to lead surfaces. Also viscosity and degree of cure during molding contributes such occurrences.This paper describes a novel extraction of Molding Process simulation results for identification of dynamically varying melt flow parameters and correlates them with the observed molding defects.

With continuous development in packaging technology, Fan-Out Wafer Level Packaging (FOWLP) has become an established approach to reach higher integration levels and geometric efficiency. Up to now, the FOWLP market has been mainly focused on compression molding using relative thick mold caps, basically as outcome from the eWLB development started by Infineon. With the wider adoption of FOWLP, also new encapsulation processes and equipment are introduced into the market. One such technology is wafer level transfer molding. This technology progresses on the current FOWLP capabilities, and achieves the thinnest mold cap possible via a process called exposed die molding, which can only be accomplished using transfer molding. This paper discusses two of the key factors that are crucial for a successful transfer molding process of thin 12" exposed wafer level packages. First, the influence of epoxy mold compound (EMC) on warpage is discussed. Contrary to compression molding, transfer molding uses materials which so far tend to induce more warpage. This paper introduces the basics behind warpage and how this can be used to select a proper EMC. Completing this section is an indicative warpage calculation using an analytical approach. Secondly, the topic of dynamic clamping in correlation to exposed die molding is discussed. A key part of exposed die molding is the critical balance between clamping force and the fluid pressure of the injected EMC. The control strategies used to maintain this balance will be discussed in this second section. Finally, an exposed die 12" wafer level molded demonstrator is presented.

Mold compound is used as an encapsulant for semiconductor chips and protecting it from environmental exposure in the forms of moisture, temperature and mechanical shock. Epoxy mold compounds are complex viscoelastic materials that change rheological properties during curing in the transfer molding process. Mold flow simulation requires correct material model parameters for accurate prediction of flow front behavior and other critical packaging issues such as mold voids and wire sweep. This modeling typically requires viscosity as a function of degree of cure, temperature and shear rate. The focus of the paper is to describe methodology to extract coefficient of the Kamal model and Castro-Macosko model that will be used for predictive mold flow finite element simulation. For reaction kinetics parameters, DSC was used to characterize degree of cure at different temperatures. Three different heating rates were used in non-isothermal tests, where the heat of curing reaction is depicted as the exothermic peak in the DSC data. In addition to curing kinetics model, rheology tests are essential to understand variation of viscosity with respect to degree of cure, temperature and shear rate. In this study, curing kinetics and rheological properties were characterized for a commercially available epoxy molding compound that is widely used for encapsulating semiconductor chips.

Recently, the fan out semiconductor packaging technology has been developed due to the demand for miniaturization and high performance of package products. The Wafer or Panel-Level Fan-Out Packages (FOPs) without package substrates such as Printed Circuit Boards (PCBs) can significantly reduce the package size and thickness and enhance electrical performances compared with conventional CSP(Chip Size Package) packages. As the Wafer or Panel-Level FOPs have been receiving more attention, FOPs related materials and processing techniques are becoming important too. At present, the transfer molding method using liquid or granular Epoxy Molding Compounds (EMCs) has been widely used to passivate chips and act as substrates. However, as wafers become larger and panel level FOPs are introduced, passivation methods using current liquid, granule, or pellet type EMCs are reaching some materials non-uniformity and thickness control limitations. To overcome these limitations, new Epoxy Molding Films (EMFs) type materials and processes have been introduced to replace the current liquid, granule and pellet type EMCs. The main roles of EMFs are to passivate semiconductor devices and act as substrates at the same time. In order to protect the semiconductor device from impact, heat, and moisture from the outside, the EMFs should have higher modulus, Glass Transition Temperature (Tg), adhesion, and lower Coefficient of Thermal Expansion (CTE). In this study, mixture of solid and liquid epoxies was used. Solid epoxy was used to provide lower CTE and higher modulus, and liquid epoxy was also used to provide higher adhesion property. After optimizing solid and liquid epoxies, the modulus, Tg, and CTE properties were significantly improved by adding the 5 µm diameter size silica filler content up to 70 wt% using. And the viscosity of EMFs was also affected by silica content. In order to improve the flow characteristics of EMFs, lower viscosities at the minimum temperature was recommended. In addition, the viscosity of the EMFs can be also decreased by the solvent content. The 10 cm × 10 cm size and the 400 µm thick EMFs were prepared for molding 10 mm × 10 mm size and 200 µm thick chips for the FOPs testing. The molding processes of EMFs were performed at various temperatures using a hot press equipment. The voids inside the EMFs were investigated using the Scanning Acoustic Microscopy (SAM) equipment to obtain optimized process conditions with no voids. And the warpage characteristics of EMFs were also observed using the Shadow Moire equipment. Finally, thermal cycle (T/C) test and 85 °C / 85% RH were performed to evaluate the effects of void, delamination, and moisture of EMFs on FOPs reliability.

This paper outlines the fundamental principles and processing characteristics of realizing application-specific "smart"' microelectronic packages utilizing fully-additive inkjet and 3D printing fabrication technologies. Standard square encapsulants are 3D-printed directly onto dies as a comparison to traditional transfer molding encapsulant techniques. This standard encapsulant is expanded through the integration of microfluidic channels directly within an encapsulant as a fully-printed solution for thermal management and fluid sensing applications with an embedded silicon die. The process flow of fully-printed partial encapsulants with subsequent capping is outlined for the realization of 3D TMV interconnects, where measurements demonstrate a low-loss versatile 3D interconnection method with adequate matching and line loss below 0.46 dB/mm up to 40 GHz. Finally, a fully-printed partial die encapsulant with TMV interconnection is presented as a proof-of-concept for process verification.

We demonstrate rapid 3D-printed molding and assembly of two-sided PDMS devices. Advancing the 3D printed transfer molding technique from single-sided microfluidics to multi-layer microfluidic manufacturing, this work utilizes the ease of 3D printing to create complementary molds with built-in alignment structures to PDMS layers and then assemble them at the end. Using this single-step double-sided molding method, we demonstrate the molding of complex geometries in PDMS — including vias, built-in alignment marks, and membrane valves — that are difficult or impossible to achieve using standard soft lithography. The membrane valves show distinctive transistor characteristic curves and a closing pressure of 200 kPa. A new stamp-bonding method is used to selectively apply liquid PDMS adhesive, demonstrating a reliable method of assembling multi-layered PDMS microfluidic devices.

This paper presents an intelligent predictive PI temperature control using particle swarm optimization - real coded genetic algorithm (PSO-RGA) for transfer molding modules in semiconductor die packaging machines. The system parameters of the transfer molding process are obtained by using the well-known reaction curve method. The best control parameters of the PI controller are offline tuned by using PSO-RGA algorithm. The set-point tracking, disturbance rejection, and robustness capabilities of the proposed method are well exemplified by conducting simulations and experiments on a real transfer mold process.

The molded underfill (MUF) process for system in package (SiP) assembly has been applied for years and is still in production. However, the shrinkage in package size, cost reduction and improving electrical performance are driving the development of dual side molding package. The development of dual side molding technology faces the challenge of moldability. The moldability is largely influenced by the increasing number of component, decreasing bump/solder pitch, and shrinkage of package area. In this work, a three-dimensional finite element model was constructed and experimentally benchmarked to simulate the void formation behavior and the allocation of voids in the package. The molding analysis result shows that the void issue occurred between thin and multi-die stack packaging that would influence the manufacturability and reliability of the package. In order to reduce the void size and the number of void, a design monitoring the ratio between compound/mold volume and mold chase layout were investigated. The results of simulation indicate that the melt front is unbalanced. The incomplete filling occurs as the ratio of compound/mold volume is over 23%. The design of implementing an over flow zone in the end of the mold chase side edge and the decrease in the space between mold chase side edge and package edge can reduce the incomplete fill. The design increases the yield rate from 92% to 99%. The results of numerical analysis indicate that the above mentioned advanced SiP package structure design would lead to lower warpage and better thermal dissipation. The enhancements in the warpage behaviors are ascribed to the dual side balance structure and the appropriate hot spot location layout. The dual side molding SiP mechanism and the design guidance for engineering application will be presented and discussed in this paper.

By changing curing accelerator and modifying the volume resistivity of epoxy molding compound (EMC), electrostatic characteristics of EMC applied package can be improved and electrostatic damage of IC device was reduced. EMC with phosphonium salt accelerator results in much lower ESD failure than EMC with phosphine salt accelerator. Because the volume resistivity of phosphonium salt applied EMC is lower than that of phosphine salt, it could easily dissipate the static electricity that generated inside of package during or after transfer molding process.

In recent years 12″ wafer level packaging has evolved from development to actual production with the eWLB product as the main example. To facilitate this, new encapsulation processes and dedicated equipment have been introduced into the market. In addition, also the wafer level package itself is evolving. Old package designs are often over-molds with thick mold caps obtained by compression molding. New designs are focusing more on mold cap thicknesses of 100 µm or less. Higher integration levels, warpage reduction and geometric efficiency are the obvious main drivers behind this. The thinnest mold cap can be achieved when the cap height is equal to the die thickness, resulting in exposed die molding, which can be accomplished with the transfer molding process. This paper highlights compound viscosity and dynamic clamping, two topics that are crucial for successful transfer molding process of thin 12″ exposed wafer level packages. Finally, an actual example of an expose 12″ wafer level molded sample is presented.

One of the present trends in microelectronic is the embedding of electronic devices directly into structural components. This integration of smart systems into hybrid and light weight structures also is a main objective of MERGE, the research cluster of excellence on Technologies for Multifunctional Lightweight Structures. The integrated silicon sensor system, also called stress monitor chip system (SMC), that allows health monitoring and failure detection in the hybrid structures is one of the MERGE demonstrators. It is capable of determining the magnitudes and the distribution of the mechanical load induced into electronics and sensor dies during embedding processes like encapsulation and moulding as well as afterwards in the service of the structural hybrid component. In the past years, the SMC system has already been shown to be highly accurate in stress monitoring during mechanical and thermal cyclic tests, in moisture swelling assessments and also during fabrication processes like transfer molding of Chip-on-Board (CoB) samples and epoxy underfilling of flip chip samples [1,2]. This paper investigates the individual process steps from the bare sensor chip up to the completion of the sensor integration in the lightweight structure regarding the induced mechanical stresses by using the SMC system.

This paper will explained detail of challenge to eliminate mold flash in mold assist film technology on flat power package. Film assist molding uses a film is coated with an adhesive layer on one side which works as a soft cushion to cover of the heat sink / paddle. This thin film also holds the lead frame paddle for prevention the paddle to tilt. Tilting of the paddle causes the mold to flow towards the paddle area during molding process and causes a reject known as “Pad Bleed”. The flash layer on the heatsink is unable to be removed by typical deflash setting, thus it prevents tin plating coverage during plating process. As a result, the solder-able pad is unable to be mounted at end customers' application circuit. The hypothesis of mold flash occurrence is due to paddle deformation caused by over-clamping during mold process. This paper will emphasis on effectiveness of combining mold design enhancement and lead frame incoming quality control to eliminate mold flash on exposed heatsink flatpower product using film assisted molding system. Distribution clamp force evenly in mold tool is major area to investigate for mold tool design enhancement. Furthermore, process control on supplier to minimize paddle tilting is another main contributor factor need to evaluate in order to maintain incoming quality. By identifying and establishing a control on a critical lead frame dimension and redesigning the mold tool, mold flash or resin bleed was able to be eliminated. The verification run showed paddle tilting is the most critical factor that needs to be controlled in order to minimize resin bleed issue, these thin resin bleed or flashes are able to be removed by the subsequent “Deflashing” process.

The quality of smart power modules strongly depends on the material characteristics of epoxy molding compound (EMC) and transfer molding process parameters. In order to predict the quality and to diminish the failure mechanisms, inline monitoring techniques in transfer molding process are essential. This work examines the inline identification of the variations in the EMC characteristics in the transfer molding process. Dielectric Analysis (DEA) is chosen as an inline technique and the influence of prolonged storage duration, moisture content and batch-to-batch variation on the characteristics of EMC are studied. In addition, the impact of molding temperature on the cure behavior of the EMC is in-situ examined. DEA results are verified and compared with the rheological and calorimetric analysis and good correlation is established.

In the broad-spectrum of 3D system integration technologies, stacking of die at wafer level is considered a promising and cost effective platform solution for 3D device and 2.5D interposer assembly. The 3D die-to-wafer (D2W) approach consists of a sequence of processes: D2W stacking, wafer-level die encapsulation ("wafer reconstruction") using e.g. wafer-level molding, Wafer thinning, Through Silicon Via (TSV) reveal and backside passivation, and finally the addition of a redistribution layer (RDL) and bumping or wafer level solder ball attach. The area explored in this paper is the 300mm wafer molding after D2W attachment. A major concern with this approach is the typically large wafer warpage after wafer level molding. This makes post-processing of the reconstructed wafers difficult with standard semiconductor equipment. Typical warpage after wafer molding of 775µm thick silicon combined with equal thickness of 775µm moldcap is around 8 mm. This is due to the large mismatch in coefficient of thermal expansion (CTE) between the materials. As a result of this large warpage, bonding the reconstructed wafer to a special carrier substrate is required to further process the wafers. This requires additional bonding and debonding equipment as well as several additional processing steps with low added value. In this paper, we will describe two different options to reduce the wafer warpage post molding. The first option is the transfer molding with exposed die. Exposed die molding reduces the amount of mold material as there is no mold compound on top of the die. It will be shown this can effectively reduce the substrate warpage to less than 1.5mm for 300mm diameter wafers. The exposed die configuration can also be used in high power application since heat sinks can be directly attached to the die backside. The second option is the transfer molding of the D2W stack together with an additional balancing wafer. The mold material is injected in a cavity formed by the stacking of the D2W and the balancing wafer. After molding, the resulting wafer warpage of the composite "D2W/W" stack is well below 200µm, compatible with semiconductor process equipment. Also important to note is the temperature independence of the warpage of this balanced stack construction. As in this approach, we can realize a direct contact between the stacked die and the balancing wafer, the balancing wafer will also act as a package-sized heat spreader. In this paper, the feasibility of Wafer Level Packaging using the transfer molding method of D2W assemblies will be demonstrated for thin mold cap, exposed die and balancing wafer approaches. The obtained experimental results are used to validate a theoretical model for predicting wafer warpage post wafer molding.

Microelectronics industry is moving towards three dimensional stacking, packaging and integration of chips to answer to the need for increased functionality, miniaturization and cost reduction of smart systems. Their increasing complexity require novel and more robust approaches for the fabrication of vertical-interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane direction. However, due to significant technology difficulties and high production costs, existing 3D technologies have limited usages. This paper describes the development of a new and robust fabrication method for dense high-aspect-ratio conductive through-polymer-vias for three-dimensional stacking, packaging and heterogeneous integration of semiconductor dies and wafers. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy molding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial which was achieved by using foil assisted transfer molding technology. Even for very thin pillars with extreme aspect ratios of >15 clean connection surfaces are obtained. Advantages of this technology are: 1) pillars are more easily exposed and wetted by the plating solution 2) faster metallization than bottom-up plating 3) no voiding nor trapping of plating chemicals 4) suitable for parallel fabrication 5) lithographically defined, enabling layout variations and extremely accurate positioning of the vias. The technology is promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging.

As we move forward to newer silicon technologies that requiring MCM dual pad leadframe design and packaging solutions with tighter process margins, it is becoming imperative to resolve ppm wire sweep failure which is critical in transfer molding process as excessive results in shorting of wires, current leakage and electrical failure. Wire sweep has been proved to be closely related to bond span, wire length, height, mold flow direction, mold gate design…etc. With the MCM dual pad leadframe design, architecture dependent mold flow phenomena and race track profile are observed and impact on wire sweep failure rate. Although the impact could be positive on wire sweep, it is considered not acceptable as it would restrict the package design and could introduce incomplete filled or void issues. Besides, it could not meet today's zero ppm mindset in the automotive and critical applications industry.

Thermomechanical reliability performance of solder bumps is a critical issue in flip chip package. Traditional underfilling process in flip chip packaging applied capillary principle to make underfill material flow into the gap between die and substrate, it was called CUF (Capillary Underfill) process. In recent years, a low cost solution called MUF (Molded Underfill) process becomes a substitution of CUF process, since the process combines underfilling and transfer molding into one process by using MUF molding compound. In this study, finite element (FE) simulation was applied to analyze thermomechanical reliability property of solder bumps in flip chip package adopted MUF process, and compared to that used traditional CUF process. Reliability tests had been performed to verify FE predictions, results showed that solder bumps with the maximum stress and strain appeared at the die corners. The corner bump with maximum stress and strain was chosen as the critical bump to estimate the thermal fatigue life. Modified Coffin-Manson equation was applied, predicted thermal fatigue life of solder bumps protected by MUF was longer that used CUF process. Various design parameters have been analyzed by FE simulation, results showed increasing bump size and molding thickness can effectively improve thermal fatigue life.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12″/300 mm diameter. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 24″x18″ or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As a process alternative also lamination as used e.g. in PCB manufacturing can be taken into account.

The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and bump pitch, especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment under the die (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound…etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different bump structure or substrate structure design, which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There are two molding flow factors will be presented in this paper. One is MUF FCCSP with different stand-off height construction (control different bump height dimension) which performs significant difference molding melt-front position. And another is substrate solder mask with different pattern design (solder mask w/ all open or finger like pattern design) which molding compound through over on solder mask pattern (solder mask with open region as 10um depth structure) and performs different melt-front pattern. From this study, we can conclude some results for improvement molding performance of MUF FCCSP during transfer molding process. The MUF FCCSP with the 50um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow that the substrate solder mask with all open structure design can get more 10um flow space under die region. Finally, the simulation results are aligned with experiments and it can be used to predict void risk.

The study focus on the process of metal electroplating on copper substrate to assemble LED chips and molding PET-copper foil to implement a flexible module with LED chips. The process can be divided into two parts,-assembling process and molding process. The LEDs are integrated on copper foil which can deal with the heat dissipation problem effectively. The metal electroplating on copper circuitry can achieve a soldered bonding to LED chips. The flexible layers of polyethylene terephthalate (PET)-copper foil are formed by two approaches-hot lamination and transfer molding. The thickness of PET-copper foil is an important parameter to the thermal design. A finite model is developed to study the effects of heat dissipation at different thickness of PET-copper foils. The results show that the flexible have a good thermal property with the thickness of PET-copper foil from 450um to 650um. Finally, a flexible model is simulated at temperature distribution with 5× 5 LEDs.

In the process of plastic packaging, void is a common defect, as the volume of semiconductor devices is becoming more and more smaller and thinner, the void problem has become the main factors influencing the reliability of product. In this study, A MEMS fingerprint sensor is taken as simulation carrier. Firstly, 3D mold flow simulation using Moldex3D is applied to the encapsulation of sensor. From the result, the distribution of the possible void in the transfer process is predicted. Secondly, under the constant condition of processing parameters, by changing the location and the amount of the gate, the flow simulation of the sensor was carried on, the purpose of finding out the influence of different gate project on the void problem for the sensor packaging. By comparing the mold flow analysis results of the different gate design project, the study reveals that the gate project has a great effect on the void problem for the sensor package. When the encapsulation model adopts one gate, the void amount of the gate in the middle of the sensor package is less than the gate in the two ends of the sensor package, due to the fact that the melt flow becomes more balanced. When the model adopts two gates, the melt flow of the model is more balance than one gate, hence the air is more easily pushed out, but the excessive pressure may be caused. Thus the gate design should be comprehensively considered with including the structure characteristics of the product and the transfer molding processes.

Moire interferometry is employed to test electronic control units, which are developed for automotive application utilizing transfer molding technology. The control units are subjected to a thermal cycle, and the two orthogonal in-plane displacement fields of the package cross-section are obtained at various temperatures. The results are used to verify and calibrate the complex 3-D finite element model of the units. The detailed experimental procedures including sample preparation are described. The modeling steps that lead to the calibrated finite element model are presented while comparing the experimental results with the numerical predictions.

Resin transfer molding (RTM) is the widely used composite material manufacturing process that produces high-strength and lightweight parts for various industrial applications. In order to manufacture defect-free parts with consistent material properties, it is important to control process parameters throughout the entire volume of the molded part. The main difficulty in the large composite parts manufacturing is unobservability of the state of material during cure process. So, model based control that use coupled models of kinetics resin cure and heat transfer in the cured composite part is the good mean to implement a controllability of RTM process. Due to a variety of newly developed components for thermoset resins used in different aircraft, navy and other industrial applications, the new kinetics models, which can satisfactory describe all stages of the resin phase transformation and evolved exothermal heat, should be developed to synthesis of the proper control law. The highlight of this work is using of genetic algorithm to identify eight parameters of new kinetic equation that was proposed to describe the complicated two stage kinetics curves experimentally obtained at the differential scanning calorimetry (DSC) of new thermoset resin developed by Formosa Plastics Co. (Taiwan) for high performance CFRP composites.