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Mobile apps are widely adopted in daily life, and contain increasing security flaws. Many regulatory agencies and organizations have announced security guidelines for app development. However, most security guidelines involving technicality and compliance with this requirement is not easily feasible. Thus, we propose Mobile Apps Assessment and Analysis System (MAS), an automatic security validation system to improve guideline compliance. MAS combines static and dynamic analysis techniques, which can be used to verify whether android apps meet the security guideline requirements. We implemented MAS in practice and verified 143 real-world apps produced by the Taiwan government. Besides, we also validated 15,000 popular apps collected from Google Play Store produced in three countries. We found that most apps contain at least three security issues. Finally, we summarize the results and list the most common security flaws for consideration in further app development.

The self-regulated learning is a goal-oriented learning strategy and it is very suitable to be applied in self-management learning for promoting learning performance of individual learner in a web-based learning environment. This study proposes a personalized e-learning system with self-regulated learning assisted mechanisms to help learners promote their self-regulated learning abilities. The proposed self-regulated learning mechanisms aim at guiding learners to become as lifelong learners who own autonomous self-regulated learning abilities.

The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of area and significant leakage power, especially at nanoscale. To remedy this situation, the paper proposed a novel approach for customizing the virtual channels allocation based on the traffic characteristics of the target application. Towards this end, the authors first develop an algorithm that calculates the port contention rates and expected bandwidth at each router in the network. Using this information, the authors add VCs only to the channels with the highest bandwidth usage. The simulation results involving synthetic and real applications show more than 40% buffer savings compared to uniform VC allocation, while achieving similar performance levels

In this paper, the authors developed a new methodology for designing a lower-error and area-time efficient 2s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, a better error-compensation bias was derived to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, the proposed fixed-width Booth multiplier was applied to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier

In this paper, intra-chip design has long been the main research area for the past years, resulting in several folds of computing power increase per year. In contrast, the speed of cross-chip connection, or even cross-system connection, has not been enhanced at the same rate, and gradually became the bottleneck of current computing systems. PCI, PCI-X, and PCI-Express epitomize the evolvement of our peripheral connecting strategy. By radical change in architecture, we successfully increase throughput of connection facilities in one autonomous system. We propose a architecture for verifying advanced switch hardware. Also successfully verify the compliance of the design under test's features to the given protocol.

In this paper, we extend our generalized methodology for designing a lower-error and area-time efficient 2's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. The generalized methodology involving three steps results in several better error-compensation biases. These better error-compensation biases can be mapped to low-error fixed-width Booth multipliers suitable for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multipliers to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.