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A key factor enabling the reduction of the thermal budget in W2W bonding integration flows is the activation sequence, consisting of cleaning and plasma treatment, used before bonding. For hybrid bonding such activation sequence needs to be selected to fulfill multiple functions: activation of the dielectric bonding surface to obtain a high bonding energy during room temperature bonding, minimize the dielectric bonding annealing temperature while avoiding exposed Cu oxidation and reducing the required annealing temperature for proper Cu-to-Cu bonding. In this paper we discuss the effect of different wafer clean methods (Deionized (DI) water and citric acid) and the effect of different plasma treatments on SiCN and Cu surfaces before bonding. The characterization techniques used include XPS, TEM, ellipsometry, SAM, OES and wafer-to-wafer bond strength testing. It is observed that Nitrogen plasma treatment can help in reducing the CuOx and a mild passivation effect of the surface is observed. Whereas on the Cu pads citric acid, used just before bonding, appears a good option, since clear effectiveness in reducing the CuOx is observed, on the dielectric it may leave some residues which can result sometimes in bonding defects. Moreover, a metric to evaluate efficient SiCN-SiCN bonding is proposed and further understanding of the physical mechanisms involved in SiCN-SiCN bonding are suggested.

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $\text{D}_{\text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $\text{Gm}_{\text{SAT}}/\text{SS}_{\text{SAT}}$ of 5.4 at 73 nm Lg.

In this paper, we investigate the tuning of a SiON tunnel oxide layer composition, in order to meet the memory operation performance requirements of a 3D NAND charge trap cell. The characteristics are compared to a VariOT ONO engineered barrier or pure SiO2. The results show that the N content increase in the SiON leads to important erase improvement at the expense of retention, therefore causing a trade-off between these two parameters. A low N content however can bring the required improvement in erase for large memory window, without compromising retention.

Potential solutions for the reliability challenges of high- k metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported. A detailed study of Negative Bias Temperature Instability (NBTI)-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-k fluorination and/or cap, metal gate) is presented. The presence of Nitrogen throughout the HKMG stack can originate either from high-k processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO 2 interface region, together with AIO x (and F) incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance.

We demonstrate an advanced a-VMCO nonfilamentary resistive switching memory cell with self-rectifying, self-compliant, forming-free and analog behavior. A BEOL-compatible process yields devices with excellent device-to-device variability, down to 40nm size. Detailed analysis of the a-Si/TiO 2 interface enables understanding the barrier resistance modulation, engineered for wider on/off window and current reduction, while preserving an excellent variability. Inner-interface engineered devices have an on/off window well above 102 and reset switching currents of down to ∼1uA for 40nm-size cells, scaling with size, without compromising reliability. Furthermore, vertical stack scaling allows to reduce the operating voltages, while preserving or tuning device figures.

A novel multi work function process is used to demonstrate up to 250 mV effective work function shifts of nMOS devices. The process use SiH 4 -soak of ALD TiN to change its barrier properties with ALD TiAl. FinFET devices are demonstrated with ∼100 mV V T -shift for 24-nm-L G devices resulting in 20× reduction in off-state leakage at unaffected sub threshold slope and improved mismatch behavior. A patterning scheme using an nMOS first RMG process is proposed and demonstrated.

Monolayer-Si-passivated Ge nFETs with high electron mobility (175 cm2/Vs at Ns=5×1012 cm−2) and superior PBTI reliability (max. Vov = |Vg-Vth| of 0.28V at 125°C) at 0.95-nm-EOT are demonstrated on a 300 mm Si wafer platform. The electron mobility is increased by optimizing the Si thickness while significant improvement in PBTI reliability is realized by band engineering using La-induced interface dipole and defect passivation using laser annealing. This is a significant step forward for the introduction of Ge nFET as high mobility device in advanced technology nodes.

To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400cm2/eV-s and 1300cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high performance CMOS applications with an emphasis on progressive EOT scaling.

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ∼5 A and ∼8 A respectively for both n and pMOS devices. The drive currents at I off =100 nA/µm with V DD =1 V is 1.4 mA/µm and 0.6 mA/µm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V T of 0.3/-0.4V, good V T -uniformity, and V T -matching and very high cutoff frequencies at ∼290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

TANOS Charge Trap Flash approach (CTF) is a candidate to replace Floating Gate approach (FG) for sub-32 nm technology node. However the main challenge for TANOS is its poor retention characteristics. In this paper, we show that by performing an O 2 anneal after Al 2 O 3 deposition the charge retention is considerably improved as well as the other memory characteristics: program, erase, endurance.

In this paper, we investigate the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1st metal layer (MG). Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence on the metal growth method than on its composition; b) studying the BTI behavior through a careful monitoring of the transients.

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 muA/mum (at VDD=1.1 V, Ioff=20 pA/mum and Jg= 100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

We show for the first time that conduction and valence band-edge effective work functions (WF) are achieved simultaneously by one single Dy2O3 capping layer on HfO2 for both nMOS and pMOS with TaCx-based metals. Low Vt's (0.23 and -0.36 V) are obtained without degrading the EOT-JG scalability and hole mobility. A model based on competing intermixes of cap/host dielectric and cap/metal is proposed to explain the positive WF shift with TaCxNy and the negative shift with TaCx as compared to the uncapped HfO2 reference. Finally, by developing a novel nitridation process to modify TaCx into TaCxNy, this work shows that single-metal-single-dielectric gate stacks are feasible, allowing cost-effective low-Vt CMOS integration.

SiON gate dielectric is optimized for general purpose 65 nm node applications by using a first nitridation approach. A process parameter screening is done where the resulting SiON films are analyzed by angle resolved XPS and non-contact probing by Quantox. Good correlation between XPS and Quantox results are found. We demonstrate also correlation between Quantox results and transistor performance. It shows that the first nitridation approach is promising for reducing gate leakage resulting in better off-state current.

The impact of nitridation anneal of Hf-silicates based metal-gated pMOSFETs on negative bias temperature instability (NBTI) is investigated. Non-nitrided stacks annealed in N2 or O2 and nitrided stacks either annealed in NH3 or exposed to decoupled plasma nitridation (DPN) are measured. For non-nitrided stacks, NBT degradation is mainly due to fast-states generation. A much enhanced NBT degradation is observed, in nitrided stacks due to the additional generation of slow states. 10 years lifetime are not reached in the nitrided stacks. A physical model, based on the field enhanced hole trapping in the dielectric during NBTI stress, is proposed to simulate slow-states generation

Phase compositions and thermal stability of different TaCx layers deposited by PVD is studied using in-situ high-temperature XRD (HT-XRD). It is found that the phase composition of the as-dep. layers and those during annealing at high temperatures strongly depends on their chemical compositions. Low carbon layers (~Ta4C) are amorphous below 700degC, and crystallize into hexagonal Ta2C in 700-900degC. At 1150degC, the Ta2C is replaced by TaSi2. Stoichiometric Ta2C are also dominantly amorphous below 900degC and starts to form cubic TaC at 900degC, and TaSi2 at 1100degC. The as-dep. TaC layers are crystalline, with a dominant cubic TaC phase. At 1000degC, the TaC is replaced by TaSi2

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.

High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO/sub 2/ reference transistors are studied in detail.

In this paper, we study the growth properties of HfO/sub 2/ on Ge by MOCVD, using TDEAH and O/sub 2/ precursors and compare the results to similar layers deposited on silicon substrates. Analysis techniques include ellipsometry, Rutherford Backscattering Spectra (RBS), transmission electron microscopy (TEM),X-ray diffraction (XRD), and time of flight secondary ion mass spectroscopy (TOFSIMS).

In this paper, in-line measurements of ultrathin gate dielectrics are reported. Various plasma nitrided oxides down to 1.5 nm EOT have been studied using in-line optical and non-contact electrical measurement techniques. The good correlation obtained with physical analysis and "classic" capacitance-voltage measurements shows the suitability of in-line measurement techniques for a first qualitative evaluation of ultrathin dielectric films.

The authors discuss Hf-Al mixed oxide characteristics, and applications to MOS capacitors and transistors. XRD an TEM analyses are performed and crystallisation behaviour analysed.

Oxide layers of metals such as Zr and Al are possible candidates to replace SiO/sub 2/ as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and we indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al/sub 2/O/sub 3/, and ZrO/sub 2/ layer is presented. We discuss the importance of a cluster tool for this application based on those process results.

Highly precise (few %) and spatially (depth and laterally) resolved (nm) measurements of dopant and carrier distributions are required to establish the actual relation between the final dopant/carrier distribution and processing steps. This paper provides a review of recent progress in the field of dopant and carrier profile characterization. Factors limiting the final accuracy and depth resolution of SIMS and spreading resistance probe are discussed in combination with recent developments such as the Nanoprofiler and Carrier Illumination which may go to the sub-nm limit. Quantitative 2D-carrier profiling is dominated by scanning probe techniques but is still limited in spatial resolution (/spl sim/10 nm).

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.