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149 results on '"Takala, J"'

3. Compile-time GPU memory access optimizations

Author

Braak, van den, G.J.W., Mesman, B., Corporaal, H., Kurdahi, F.J., Takala, J., and Electronic Systems

Subjects
Instruction set, CUDA, Coprocessor, Computer architecture, Computer science, CUDA Pinned memory, Graphics processing unit, Parallel computing, Compiler, computer.software_genre, computer, Bottleneck, Compile time
Abstract

In the last three years, GPUs are more and more being used for general purpose applications instead of only for computer graphics. Programming these GPUs is a big challenge; in current GPUs the main bottleneck for many applications is not the computing power, but the memory access bandwidth. Two compile-time optimizations are presented in this paper to deal with the two most important memory access issues. To describe these optimizations, a new notation of the parallel execution of GPU programs is introduced. An implementation of the optimizations shows that performance improvements of up to 40 times are possible.

Published
2010

4. Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM

Author

Wolkotte, P.T., van de Burgwal, M.D., Smit, Gerardus Johannes Maria, Nurmi, J., and Takala, J.

Subjects
Flexibility (engineering), Computer science, Computation, Fast Fourier transform, CAES-EEA: Efficient Embedded Architectures, EC Grant Agreement nr.: FP6/001908, Power of two, Energy consumption, Parallel computing, ARM architecture, Reduction (complexity), General purpose, METIS-238270, IR-66563, EWI-7963
Abstract

Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.

Published
2006

9. Multiple-symbol parallel decoding for variable length codes

Author

Nikara, J. (author), Vassiliadis, S. (author), Takala, J. (author), Liuha, P. (author), Nikara, J. (author), Vassiliadis, S. (author), Takala, J. (author), and Liuha, P. (author)

Abstract

Electrical Engineering, Mathematics and Computer Science

Published
2004

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