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A 1.2 V, 1.8 Gb/s/pin 16Tb-NAND flash memory multi-chip package incorporating with 16-dies of 1-Tb NAND flash memory and the 3rd generation F-Chip is proposed. The proposed F-Chip is developed to meet the performance requirements of high capacity storage devices that adopts PCIe Gen 4 host interface for faster data throughput. It is implemented with Toggle 4.0 standard on dual bi-directional transceiver architecture to achieve maximum valid data window on SSD channels. Also, it facilitates training between F-chip and NAND using on chip DLL and BIST to achieve sufficient signal integrity on in-package channel for 1.8Gb/s/pin. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

In this paper, the modified annular ring slot antenna is proposed for 2.4/5-GHz dual WLAN band operation. The higher order resonant modes in the annular ring slot are used to control the second operating frequency. The proposed antenna is printed on a FR-4 substrate, and has dimensions of 50 times 50 times 1.2 [mm] with a ground plane. The frequency ratio of the two operating frequencies can be adjusted from 1.97 to 2.64 with geometric values. The measured impedance bandwidths (VSWR

A new protective relaying algorithm that observes the trend of terminal voltage and differential current, and identify the disturbance-fault, inrush, over-excitation-is developed. Various tests have shown that it is very effective even during the first cycle of the transient and works for any type of transformers. The average operation time is less than a half cycle.