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Voice conversion (VC) is a task to transform a person's voice to different style while conserving linguistic contents. Previous state-of-the-art on VC is based on sequence-to-sequence (seq2seq) model, which could mislead linguistic information. There was an attempt to overcome it by using textual supervision, it requires explicit alignment which loses the benefit of using seq2seq model. In this paper, a voice converter using multitask learning with text-to-speech (TTS) is presented. The embedding space of seq2seq-based TTS has abundant information on the text. The role of the decoder of TTS is to convert embedding space to speech, which is same to VC. In the proposed model, the whole network is trained to minimize loss of VC and TTS. VC is expected to capture more linguistic information and to preserve training stability by multitask learning. Experiments of VC were performed on a male Korean emotional text-speech dataset, and it is shown that multitask learning is helpful to keep linguistic contents in VC., Comment: 4 pages, 3 figures, submitted to ICASSP2020

This paper presents a comparison between simulation and experimental results of a brushless AC motor with sinusoidal back-EMF (Electromotive Force)according to the current shape. The prototype high-speed BLAC is designed for an electric turbocharger which rated output is 100,00rpm and 3kW. Because of the position sensor and field weakening control in the high speed region, square wave current control scheme based on the hall sensor signal is considered to operate the designed highspeed BLAC. Based on the current shape of the BLAC, it can be seen that the acceleration and vibration characteristics change accordingly to the output torque and the torque ripple. The performance and efficiency corresponding to the controlled current shape are analyzed for various operating conditions. A better control method solution for high-speed application is presented in this paper and the results are compared.

In this paper, we propose event detection based on deep learning using audio and radar. The proposed event detection technique combines the two deep-learning models based on the audio signal and radar signal. The data set used research is consist of five indoor events., It showed better performance than the event detection using audio or radar single data.

In this paper, we introduce a robot-assisted remote ultrasound imaging system connected to 4G LTE mobile internet. Unlike the wired internet connection with the static IP addresses, mobile internet connection makes it easy to move the slave system and allows a remote connection to wherever mobile communication is available, thus enabling tele-echography even in poorly equipped internet facilities. In order to connect the slave system with the master system through 4G LTE mobile internet, SIP and STUN server were included in the network part of the robot-assisted tele-echography system. In the experiment, the developed system was tested for the network performance between the urban hospital and the remote location separated about 250 km away. In addition, RTT test was performed to measure the speed of data transmission for remote robot control under 4G LTE mobile Internet. Based on the experimental results, the average RTT in the mobile Internet was 45.67 ms and the standard deviation is 7.17 ms, which shows that the communication speed is lower than the wired Internet connections and is also somewhat unstable. In addition, we examined that the tracking error between the slave robot and the master device with respect to different types of network configuration. The average RMSE by mobile internet was increased to 3.8 mm from 3.1 mm by the wired Internet. However, 30Hz of remote ultrasound imaging could be performed, and unidirectional remote control was available at the communication speed of up to 44 Hz. Therefore, there is no problem in utilizing the mobile Internet in the current robot-assisted tele-echography system.

A large number of people suffer from spinal diseases, or so called back pain. Although numerous medical devices and therapies have been developed for treatment, back illnesses remain a problematic issue. Recently, the spinal traction has been reported to have a positive effect on spinal diseases, and an intelligent machine which stimulates the spine has been developed. This paper presents a theoretical study of how appropriate force can be applied from the spinal traction system to the spine. The system is designed to stimulate the spine, and the scale of force is controlled by the patient's biological status, such as blood pressure or heart rate. The theoretical force is compared to experimental results, and shows that the force is highly correlated to the theoretical derivation. The proposed approach can be utilized to customize the force on the spine based on the patients' weight and the angle of the spinal traction machine.

In order to structure the complex nature of the significant wave height time series, Autoregressive Integrated Moving Average model of order (p,1,0) was applied. Each step which is essential for precise modeling is covered comprehensively. First, the stationarity of given time series of SWH with its 1st order difference were checked. Akaike's Information Criteria and Bayesian Information Criteria for each model were calculated thereafter, in order to sort tentative models. And then, Ljung-Box tests were carried out on the residuals of each model to verify whether the residuals show autocorrelation. Through these processes, the optimal models for each time spans were measured. Furthermore, forecasted time series of significant wave height from Monte-Carlo simulations of each model have proven the utility of the proposed method as it mostly complies with the observed time series of significant wave height.

Real-time multi-object tracking is one of the most challenging problem in computer vision. Based on integer linear programming (ILP) formulation for object tracking [1, 2], we propose the greedy algorithm for real-time multi-object tracking. The experimental result shows that the performance of the proposed algorithm is competitive to the previous state-of-the-art algorithms on off-line video data, and its running time is also sufficient for analyzing the tracks of object in real-time video data.

This paper proposes a PCB design method of highspeed signal interface that is robust against electrical overstress (EOS). Surge and electrostatic discharge (ESD) waveforms as defined in the International Electro-technical Commission (IEC)61000-4 standard were used for EOS input waveforms from the connector to the printed circuit board (PCB). Signals in the Tx line of the universal serial bus 3.0 (USB3.0) interface were simulated to analyze the role of the diode and capacitor in the interface circuit, and it was found that the proposed capacitor and diode coordination shows the best combination of schematics for the prevention of EOS. Experiments with an interface circuit in a laptop computer were also performed and the results show that the effectiveness of proposed design is valid.

This paper considers a joint learning algorithm of foreground region labeling and depth ordering for 3D scene understanding. Given an object-level segmentation, the proposed algorithm classifies each region as either foreground or background while simultaneously infers the relative depth orders between every adjacent region pairs. For this, we consider a graph where regions are considered as nodes while boundaries between adjacent regions as edges, and the problem is formulated as jointly assigning binary labels to every nodes and edges via maximizing a unified linear discriminant function, under the constraints that make the resulting depth order to be always physically plausible. Instead of inferring region and edge labels separately, we infer them jointly by grouping them as a single variable referred to as triplet. Then, the problem is reformulated as multi-class triplet prediction to penalize the inconsistent labeling of regions and edges in a soft manner. As the discriminant function is linear, the parameters can be learned with structured support vector machine(SSVM), and efficient inference using linear programming relaxation is possible. Experimental results show that the proposed joint inference algorithm improves both foreground region labeling and depth ordering performances.

In this paper, a cepstral analysis based approach to measuring the depth of anesthesia (DoA) is presented. Cepstral analysis is a signal processing technique widely used especially for speech recognition in order to extract speech information regardless of vocal cord characteristics. The resulting index for the DoA is called index based on cepstral analysis (ICep). The Fisher criterion is engaged to evaluate the performance of indices. All analyses are based on a single-channel electroencephalogram (EEG) of 10 human subjects. To validate the proposed technique, ICep is compared with bispectral index (BIS), which is the most commonly used method to estimate the level of consciousness via EEG during general anesthesia. The results show that ICep has high correlation with BIS, and is outstanding in terms of the Fisher criterion and offers faster tracking than BIS in the transition from consciousness to unconsciousness.

In this paper, an adaptive linear equalizer with an inter-symbol interference (ISI) level measurement using a periodic training pattern is presented. The compensation level of the equalizer is determined by measuring ISI level and fed back to the feed-forward equalizer. The proposed algorithm is verified with a 100-cm flexible flat cable (FFC) at 10Gb/s data rate using a 90nm CMOS process technology. Compensation range is from 15 dB to 33 dB with a tuning range of 18 dB, and the current consumption is 7.6mA at 1 V power supply.

This study introduces a system to merge three different Sea Surface Temperature(SST) data obtained from multi-satellite sensors. SST is important variable to understand interaction between the atmosphere and ocean. In this study, merging method is filling-in according to SST accuracies which each satellite has. The sensors that produce merged SST field data are NOAA/AVHRR (National Oceanic and Atmospheric Administration/Advanced Very High Resolution Radiometer), Terra & Aqua/MODIS (Moderate Resolution Imaging Spectro-radiometer) and MTSAT-1R (Multi-functional Transport Satellite). Errors, numerical subtractions, between satellite and buoy data were expressed to an error graph.

In this paper, we present a low-power non-coherent amplitude shift keying (ASK) and phase shift keying (PSK) demodulators with inductive power self-recovery system, and the data-clock recovery circuit for implantable biomedical devices. Both circuits use different coupling factors k from 0.1 to 0.5 in ASK and 0.5 in PSK for inductive link The recovered power regulator that consists of a beta multiplier reference (BMR) with band-gap uses the bridge rectifier output as an unregulated DC input, and produces from 1.73 to 1.8 V regulated output for the demodulator with 2 MHz carrier. The PSK demodulator uses a new demodulation method that uses signals from two differential comparators with low-pass pre-filtered (LPPF) and high-pass pre-filtered (HPPF) outputs for detecting phase changing edges to recover data and clock signals. The full wave detecting signals are used as differential inputs in LPPF comparator of the ASK demodulator. The results of the demodulators with the self-power supply show up to less than 62 μW and 115 μW power consumption in ASK and PSK at 1 Mbps data transfer rate.

This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

In this paper, an entropy based method for quantifying the depth of anesthesia from rat EEG is presented. The proposed index for the depth of anesthesia called modified Shannon entropy (MShEn) is based on Shannon entropy (ShEn) and spectral entropy (SpEn) which are widely used for analyzing non-stationary signals. Discrimination power (DP), as a performance indicator for indexes, is defined and used to derive the final index for the depth of anesthesia. For experiment, EEG from anesthetized rats are measured and analyzed by using MShEn. MShEn shows both high stability and high correlation with other indexes for depth of anesthesia.

Many Search Based Software testing (SBST) have been proposed and experiments show that they can generate effective test data. However, a meta-heuristic search (MHS) algorithm in these techniques incurs considerable computation cost to evaluate fitness values, which results in huge test case generation cost. In this paper, we propose a more effective fitness evaluation technique based on Fitness Evaluation Program (FEP). FEP, derived from a path constraint of SUT, is introduced as a special program for evaluating fitness values. We implement a test generation tool, named ConGA, and apply it to generate test cases for C programs for evaluating efficiency of the FEP-based test case generation technique. The experiments show that the proposed technique can reduce significant amount of test data generation time on average.

This paper presents a DLL(Delay Locked Loop)-based CDR(Clock Data Recovery) design with nB(n+2)B data formatting scheme. Due to the proposed data formatting scheme, the CDR does not require the external reference clock. The proposed nB(n+2)B data formatting scheme is done by inserting the ‘01’ pattern in every N-bit data. To prove the feasibility of the scheme, a 1.7Gbps CDR is designed, simulated and fabricated. The proposed CDR achieves less jitter due to the DLL structure. The proposed 1.7Gbps CDR with the 10B12B data formatting consumes approximately 8mA under 3.3V power supply using 0.35µm CMOS process.

This paper presents a clock and data recovery (CDR) circuit that supports dual data rates of 5.4Gbps and 3.24Gbps for DisplayPort v1.2 sink device. The quarter-rate linear PD in the proposed CDR reduces jitter by enhancing the up and down pulse width. A charge pump (CP) is designed to compensate the different up and down pulse width of the PD and to reduce the current mismatch and power consumption. A voltage controlled oscillator (VCO) is designed with a “Mode” switching control for operating frequency selection. The measured RMS jitter of recovered clock signal is 3.0ps and the peak-to-peak jitter is 24.89ps under the simulation of a 231−1 bit-long pseudo random bit sequence (PRBS) at the bit rate of 5.4Gbps. The chip area is 1.0mm × 1.3mm and the power consumption is 117mW from a 1.8V supply using 0.18µm CMOS process.

Here we report hybrid organic/inorganic quantum-dot LED with high-performance. Use of sol-gel TiO 2 as electron transport layer allows the device to be fabricated with all-solution process and have more efficient energy band structure for carrier injection and confinement. Quantum dot layer was crosslinked and thermally annealed to enhance the device performance. Quantum dot crosslinking not only made all-solution process feasible but also enhanced hole injection by shifting valance band of 0.3∼0.6 eV, resulting in better charge balance. The degree of band-level shift depends on the asymmetric adsorption of ligand which might cause the dipole alignment of QD layer through the hole transport. The resulting device showed a high luminance (>10,000 cd/m2), low turn on voltage (1.9 V), and the high power efficiency (2.41 lm/W). Incorporation of the technology into a display device with an active matrix drive backplane for the first time suggests that the approach is promising for high performance, easy-to-fabricate, large area displays and illumination sources.

A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110µsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL driver, and a stepped write WL technique.

Titanium and Titanium alloys have been widely used in aerospace and automotive industries and medical applications due to their high strength-to-density ratio, excellent fatigue and corrosion resistances. Especially metastable β titanium alloys are increasingly attractive for commercial use in high strength structural components because of their excellent cold formability. Some β titanium alloys are being used as bone implants under biomechanical loading condition because of its excellent biocompatibility and mechanical properties. An essential requirement for an artificial material to bond to living bone is the formation of a bonelike apatite layer on its surface in body environment. The formation of a bone-like apatite surface layer can be reproduced in an acellular simulated body fluid (SBF) with ion concentration nearly equal to those of inorganic part of human blood plasma. In this study, biomimetic apatite deposition behaviors in various SBF conditions and stress-strain responses of Ti-15Mo-3Nb-3Al-0.2Si alloy were examined.

Providing high quality panoramic video over Internet, mobile and broadcasting areas, requires a suitable video codec that satisfies both highcompression efficiency and random access functionality. On the user side, high compression efficiency is necessary to enable video streaming of high-volume panoramic data; the random access functions allow the user to move the viewpoint and direction freely. In this research, we introduce the cell concept for compression efficiency and random access functionality and propose a high-speed algorithm for the encoder and decoder of wide screen panoramic images.

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

When a washing machine is rotating with the laundry in it, it tends to lean to one side. This tendency causes a serious vibration. The balance of a washing machine plays an important role in order to reduce the vibration by injecting the sand or the salt water into the balance of washing machine. The hot plate welder is used to prevent the contents from outflowing. The thermal characteristics of the hot plate and the balance have to be considered for reducing the defects in plastic welding. The hot plate welder brings about many problems that may lead to an accident. The workers are protected by the loading/unloading system for the washing machine balance in the hot plate welder. This system requires direction recognition and location information of the balance. In this paper, thermal analysis of the hot plate welder for the washing machine balance is performed. The heat source of the hot plate welder plays a really important role in welding the washing machine balance. The temperature distribution of the hot plate and that of the washing machine balance are obtained by finite element analysis. The temperature of the hot plate is measured by the infrared temperature sensor in order to find the thermal contact resistance. The thermal strain of the plastic balance is predicted by thermal-structural coupled analysis.

The new packaging approach for crystal resonator with quartz crystal is described in this paper. We designed and optimized the structure of wafer level crystal unit package for low cost and high performance with 2.0×1.6×0.45 mm3 size. The crystal unit package is reduced in size and thickness by using a 4" wafer level package technique of general semiconductor process. Traditionally, the package substrate of crystal unit device used ceramics order's HTCC (high temperature co-fired ceramic) and metal lid. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The AuSn eutectic bonding between glass package wafer and Si cap wafer that is etched using DRIE (deep reactive ion etch) process protects the quartz blank mechanically and encapsulates high vacuum state. The frequency and impedance performance of wafer level crystal unit in comparison with conventional crystal unit devices is characterized.

In this paper, a 5-Gb/s receiver with adaptive equalizer and clock and data recovery(CDR) for serial link interface is proposed. In order to operate adaptively at 5-Gb/s data rate, LMS algorithm uses two internal signals from slicers which does not have an effect on gain boosting performance. In addition, this scheme enables it to operate without passive filter since two internal signals of slicers has a similar DC magnitude. The proposed adaptive equalizer in this receiver can compensate up to 20-dB and operate in various environments, which are 15-m shield twisted pair(STP) cable for DisplayPort and flame retardant 4(FR-4) traces up to 60-inch adaptively. This work is implemented 0.18-mum 1-poly 4-metal CMOS technology. Power dissipation of the equalizer is only 6-mW and it occupies 200 mum times 350 mum. Total power dissipation of the combined CDR is 164-mW (including output buffers) and operating range is available up to 5-Gb/s.

Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm3 size and results of electrical performance is evaluated.

Security systems are complex systems that perform multiple functions such as position locating of personnel, entry/exit management of personnel, entrance management, monitoring, logging, tracing, authentication, and authorization. This paper attempts to establish a security system using aspect oriented programming (AOP). Because it is possible to establish a system by completely separating the business logic and security logic of a system using AOP, there is the advantage of being able to clearly identify the roles of each module. Also, doing so enables the establishment of a more flexible system through leveraging the innate advantages of AOP, which are expansion of code reusability and implementation of efficient features.

Wafer level surface acoustic wave (SAW) filter package, 0.8times0.6 mm2, is drilled by laser via process. Via formation for interconnection is based on smaller package manufacture. LT (LiTaO3) which is base material of SAW filter is difficult to drill a small via by RIE (Reactive Ion Etching) because the RIE gets a very small etch rate and has wafer broken issue by thermal heating. So, our previous review is focused on the sand blasting process for via formation. However, there is limitation on via size and via depth and makes a leakage path at interface of Cu and via side wall by roughness and micro crack after electroplating. So, study on the laser via technology for meeting a design rule requests below 30 um via hole size and over 110 um depth. That gives a good solution of via formation for our package. However, the laser via makes the secondary issues such as debris and via shape, which disturb the electroplating of via inside. Overcoming these troubles and removing debris of via inside by new cleaning method are applied to general etching steps. Finally, we make a 0.8times0.6 mm2 SAW filter using laser via with etching steps compared with it using normal laser process. The result of electrical performance and laser process for wafer level SAW filter package is also discussed.

Device driver is the most important software of operating system to interact with hardware devices. As an essential part of operating system, device drivers must be reliable and efficient, because wrong operation can make a fatal system error and hardware performance is depends on the device driver. Therefore, it must be developed carefully and considered to be difficult to develop. Previously, we presented an automated source code generation framework and tool for Linux device drivers. In this paper, we present enhanced code generation framework for domain-specific device driver by usage domain and show detailed view of implementation.

This paper presents a scalable dual-field Montgomery multiplier based on a new multi-precision carry save adder (MP-CSA), which operates in both types of finite fields GF(p) and GF(2m). We also design a word-level adder for cryptographic applications by reusing the proposed multiplier circuit. The proposed Montgomery multiplier has roughly the same timing complexity and the advantage of reduced chip area requirements compared with the previous result.

A motive toolbox of reconfigurable modules is described to extend capabilities of the TerminatorBot. The robot can be statically reconfigured with both sensors and actuators for particular applications by way of the morphing bus. The morphing bus is a parallel bus that adapts to the modules connected. A software tool is provided to aid the user in static configuration. This paper focuses on three modules, still in the prototyping stage, for adding bulk motive force to the robot in a hybrid fashion. Methods of channeling the motive force are also discussed.

This paper presents the new type of SOA Framework that can provide smooth service in the B2C and C2C environment unlike its predecessor which mainly considers the B2B environment. To this end, this SOA has been established with the use of JXTA that is emerging as the next-generation P2P Platform. The Framework presented here includes the basic functions of the SOA Framework. In addition to that, it is made easier to provide and tap into services compared with other frameworks while addressing security issues that may occur when using the service. One of its strong points is that each peer can not only be a service provider, a service client but also play a role as a service registry at the same time since P2P has been established in the form of a platform.

To fulfil metrological requirements of profiling aspheric surfaces, a very-large-scale phase measuring interferometric system is presented that has been developed at Korea Advanced Institute of Science and Technology. The measurement system comprises an interference microscope probe mounted on the z-axis and a precision xy-stage. The probe operates with principles of white light scanning interferometry to sample three-dimensional data in discrete form with a sub-nanometer resolution. A 640x480 pixel array CCD camera is used, thus the area of a single patch is limited within 0.64x0.48 mm with 1.0 /spl mu/m lateral resolution. The stage is controlled in the xy-directions with the aid of three plane mirror type heterodyne laser interferometers with 2.5 nanometer positioning resolution.

Wireless Local-Area-Networks (WLAN) should operate in multipath environments because it is used in inside office buildings or factories. Therefore Complementaty Code Keying (CCK) has been adopted as the IEEE801.11b Standard for WLAN's at 2.4 GHz due to its good performance in multipath. In this paper, the better performance and the less complex hardware structure has been accomplished through the modulator formation with differential-modulator and demodulator using phase-detector. It was more effective rather than using RAKE Receiver in WLAN. The phase-detector used in the demodulator utilized the characteristic of CCK, automatic weighting of the subchannels; erroneous channels with low amplitudes will only give a minor contribution to the phase estimates. And additional iterative methods could determine more exact phase value. Therefore it could get better performance. The proposed structures lead BER performance to improve approximately 2 dB and are simpler than those of RAKE Receiver.