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Minaei, Shahram (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2018; Florence; Italy; 27 May 2018 through 30 May 2018. Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.

Minaei, Shahram (Dogus Author) -- Conference full title: 2017 European Conference on Circuit Theory and Design (ECCTD); Catania; Italy; 4-6 September 2017. In this paper, a new electronically controllable current-mode instrumentation amplifier (CMIA) is presented. The proposed CMIA is based on only two electronically tunable second-generation current conveyors (ECCIIs). It does not need any passive element which makes it highly suitable for integration. More interestingly, high CMRR is achieved without the need for matching between active elements. Its input and output signals are current and it enjoys low input and high output impedances, respectively. Due to the inefficiency of the existing ECCIIs, a new ECCII circuit is also designed to be used in the proposed CMIA structure. PSPICE simulation results using 0.18μm TSMC CMOS technology and supply voltage of ±0.9V, shows CMRR of 42dB and fixed -3dB bandwidth of 68MHz for differential-mode gain ranging from 0dB to 27dB.

Minaei, Shahram (Dogus Author) -- Conference full title: 2016 39th International Conference on Telecommunications and Signal Processing, TSP : June 27-29, 2016, Vienna, Austria. A New CMOS resistor based current mirror with extremely low voltage requirement at input (in the range of a few mV) and output voltage requirement of about one Vds is presented. The proposed structure combines the advantages of wide input swing, wide output swing, large output impedance, low input impedance and high linearity altogether, which make it attractive for high performance low-voltage and low power applications. Pspice simulations show a very low THD of -42.2dB from a single 0.9V supply in 0.18μm, input impedance of 239Ω, output impedance of 1.2MΩ and power dissipation of only 180μW. Interestingly, the input and output voltage requirements are only 10mV and 0.1V respectively.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) In this paper an NMOS based sinusoidal oscillator is presented. The circuit is constructed with voltage-mode (VM) NMOS-based analog adder and subtractor circuits which respectively perform V1+V2 and V1-V2 operations on the input voltages. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for the adder, six for the subtractor). Another significant advantage of the proposed circuits is that no external passive components are being used. The post-layout simulations of the proposed oscillator circuit have been executed using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: European Conference on Circuit Theory and Design, ECCTD 2015; Trondheim; Norway; 24 August 2015 through 26 August 2015 In this paper, a new RC circuit realization of voltage-mode (VM) first-order all-pass filter (APF) is presented. The proposed VM APF scheme is composed of a single grounded capacitor, three resistors with one being negative. The main advantage of the circuit is the common ground terminal between the input and the output. For proper functionality passive element matching is required and the negative resistance is implemented with Arbel-Goldminz operational transconductance amplifier. The theoretical results are verified with SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters. Institute of Electrical and Electronics Engineers Inc.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, logarithmic, divider and exponential function generator circuits. It is proposed a solution for implamentation of the analog logarithmic and exponential functions, which are not an easily accessible characteristic in CMOS technology, as well as their integration in a configurable cell. Current-mode implementation of the circuits leads to straightforward and intuitive configurations. To study the performance of the circuit, effects of channel-length modulation as well as the mismatch in the threshold voltages are thoroughly discussed. The proposed circuits are designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. MATLAB results validate the simulation results which are obtained by HSPICE.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 μm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with ±0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 μW power.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2015; Lisbon; Portugal; 24 May 2015 through 27 May 2015 In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFS) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFS as useful active filter parameter, the proposed filter employs only a floating capacitor as external passive component. The pole frequency of the proposed resistorless circuit can be tuned via mutual change of input intrinsic resistance of CFS while the filter pass-band gain by means of gain of ACA. The theoretical results are verified by SPICE simulations, where TSMC 0.18 μm level-7 SCN018 CMOS process parameters were used.

Conference: 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) -- Location: College Station, TX -- Date: AUG 03-06, 2014 In this paper, a new realization of a first-order voltage-mode (VM) All-Pass Filter (APF) using a grounded capacitor, three resistors, and a single Current Follower (CF) with non-unity gain is presented. The number of external resistors in the proposed VM APF can be reduced to two by considering the input intrinsic resistance of the CF as a useful active parameter. In comparison to the second-generation current conveyor-based current follower implementations employing large number of metal-oxide-semiconductor field-effect transistors (MOSFETs), here the used CF is composed of only four MOSFETs. Hence, it is favorable for low-voltage low-power circuit design. The APF was designed at pole frequency of 9.8 MHz with 112 mu W power consumption using PTM 90 nm level-7 CMOS process BSIM3v3 parameters and with +/- 0.5 V DC voltages. SPICE simulation results are included to support the theory. IEEE; IEEE Circuits & Syst Soc; Texas A & M Univ.

In this paper, two new single-input five-output (SIFO) voltage-mode (VM) second-order universal filters are presented. The proposed filters employ two triple-output second-generation current conveyors (TO-CCIIs) as active elements, five resistors and two grounded capacitors. The proposed filters provide all of the standard filter responses (i.e. low-pass, band-pass, high-pass, notch and all-pass responses) simultaneously. The non-ideal gain and parasitic impedance effects of the active elements on the transfer functions of the filters are investigated. SPICE simulation results with TSMC 0.18 μm technology parameters are given to verify the performance of the proposed filters. © 2012 IEEE.

Field-programmable gate-array (FPGA) implementations of binary amplitude-shift keying (BASK), binary frequency-shift keying (BFSK), and binary phase-shift keying (BPSK) digital modulators are presented. The proposed designs are aimed at educational purposes in a digital communication course. They employ the minimum number of blocks necessary for achieving BASK, BFSK, and BPSK modulation, and for full integration with the other functional parts of the Altera Development and Education (DE2) FPGA board. The input carrier signal and the bit stream (modulating signal) are user controllable. These digital modulators were developed and compiled to a Verilog Hardware Description Language (HDL) netlist, and were later implemented into an Altera DE2 FPGA board. The functionality of these digital modulators was demonstrated through simulations using the Quartus II simulation software, and experimental measurements of the real-time modulated signal via an oscilloscope.

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-mu m technology.

Minaei, Shahram (Dogus Author) In this paper, a new voltage-mode first-order all-pass filter with high-input and low-output impedances is presented. The circuit is composed of single universal voltage conveyor (UVC), single capacitor, and an n-channel MOSFET-based voltage-controlled resistor (VCR) that allows to control the pole frequency 0 of the filter electronically. No component-matching constraints are required and it has low sensitivity. The proposed filter provides both of inverting and non-inverting outputs at the same configuration simultaneously. The non-idealities of the proposed circuit are also analyzed. The theoretical results are verified by SPICE simulations using TSMC 0.35 m CMOS process parameters.

In this paper, a new fully CMOS four-quadrant multiplier based on plus-type second-generation current conveyors (CCII+s) is presented. The proposed circuit employs only two CCII+s and two NMOS transistors as active devices, without the need for any external passive elements. Functionality of the new circuit is demonstrated through SPICE simulations performed using 0.25 mu m CMOS process technology parameters. In addition, simulation results of an amplitude modulator realized with the proposed multiplier are included.

Shahram Minaei (Dogus Author) -- Communication Software and Networks (ICCSN), 2011 IEEE 3rd International Conference on: date, 27-29 May, 2011 In this paper new high performance current-mode precision full-wave rectifier using the current differencing transconductance amplifier (CDTA) is presented. To analyze the behavior of the proposed rectifier, the frequency-dependent RMS error and DC transient value are evaluated for different values of input current amplitudes. The SPICE simulations are also included that show the feasibility to rectify signals of frequency 10 MHz and beyond with no or minimal distortion.

Yıldız, Merih (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Minaei, Shahram (Dogus Author) -- Deniz, Engin (Dogus Author) A recently built IC which implements a CMOS tunable classifier circuit is introduced and test results of an application are presented. The classifier circuit parameters are determined for Iris data set with an algorithm based on Fisher's linear discriminant analysis (LDA); the data is first soft then hard classified. The proposed circuit was fabricated using CMOS AMS 0.35 μm process parameters and its performance experimentally tested with Iris data. The layout of the IC also includes current conveyors and current buffers. This work is part of project 106E139 supported by the Scientific & Technological Research Council of Turkey (TÜBİTAK).

Yıldız, Merih (Dogus Author), Minaei, Shahram (Dogus Author) -- Full conference title: 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference : (NEWCAS-TAISA 2009) ; Toulouse, France, 28 June - 1 July 2009 In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of linearly weighted circuits (LWC) and CMOS core circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 mum AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.

Minaei, Shahram (Dogus Author) -- Full conference title: 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference : (NEWCAS-TAISA 2009) ; Toulouse, France, 28 June - 1 July 2009 A high performance CMOS current differencing buffered amplifier (CDBA) is presented in this paper. The proposed circuit operates with the power supplies of plusmn0.75 V and consumes low power. HSPICE simulations show that the proposed CDBA provides better performance in nearly all parameters than the previous ones. As an application example, a second-order notch filter is chosen from the literature to demonstrate the performance of the proposed circuit.

In this paper a CMOS implementation of a multi-input data classifier with several output levels and a different architecture is presented. The proposed circuit operates in current-mode and can classify several types of analog vector data. The classifier circuit's new architecture consists of the interconnections of core cells each possessing a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using 0.35 mum TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.

In this work, a new multi-input single-output voltage-mode filter realizing low-pass, band-pass, high-pass, notch and all-pass characteristics depending on the input signal selections is presented. The filter employs minimum number of passive elements, and does not need passive element matching. The presented filter has adjustable angular resonance frequency and quality factor, and low active and passive element sensitivities.

In this paper, a new CMOS high-performance electronically tunable second-generation current conveyor (ECCII) is presented. The current gain of the proposed ECCII can be controlled electronically by adjusting the ratio of dc bias currents of the ECCII. The output terminal of the proposed ECCII has high impedance, which enables easy cascadability. Also, as an application, the proposed ECCII is used for realizing a universal current-mode filter. The filter realizes low-pass, bandpass, and high-pass responses simultaneously. The low-pass response is obtained at high impedance output and its gain can be independently tuned by changing the current gain of the relevant CC. SPICE simulation results using TSMC 0.35-/spl mu/m CMOS process model shows excellent performance for the proposed ECCII. The proposed circuit consumes average power of 6.6 mW using /spl plusmn/1.5-V supply voltages.

In this paper, a new active circuit for realizing lossless floating inductor using current controlled conveyors (CCCIIs) and single capacitor is presented. The proposed inductance simulator can be tuned electronically by changing the biasing currents of the CCCIIs. As an application, the proposed floating inductance simulator is used to construct a fifth-order low pass filter. The theoretical analysis is verified by SPICE simulation results.

In this paper a new current transfer function synthesis using CTMOS high performance electronically tunable second-generation current conveyor (ECCII) is presented. All the coefficients of the transfer function can be independently tuned through the variable current gain of the ECCIIs. Based on the principles upon which the general transfer function structure was constructed, a universal current-mode filter is proposed which implements the lowpass, bandpass and highpass responses simultaneously in high output impedances. Thanks to the tunability of the ECCIIs, the parameters omega(o) and Q of the filter can be adjusted electronically. SPICE simulation results using MIETEC 0.5 mu m CNIOS process model are included to verify the theory.

This comment, relates to a recently published paper by M. Sagbas and K. Fidanboylu (see ibid., vol.40, p.2-4, 2004) which presents a current-mode second-order universal filter for realising lowpass, bandpass and highpass responses. This filter employs two second-generation current controlled conveyors (CCCIIs) and two capacitors. It is shown here that this circuit is not new, simply derived from another filter proposed by S. Ozoguz and C. Acar (see ibid., vol.33, p.948-9, 1997), employing CCCIIs instead of second-generation current conveyors (CCIIs).

This paper presents new circuits for realizing both current-mode and voltage-mode proportional-integral- derivative (PID), proportional-derivative (PD) and proportional-integral (PI) controllers employing second- generation current conveyors (CCIIs) as active elements. All of the proposed PID, PI and PD controllers have grounded passive elements and adjustable parameters. The controllers employ reduced number of active and passive components with respect to the traditional op-amp-based PID, PI and PD controllers. A closed loop control system using the proposed PID controller is designed and simulated with SPICE. I. INTRODUCTION The proportional-integral-derivative (PID), proportional- integral (PI) and proportional-derivative (PD) controllers with adjustable parameters are widely used in many industrial control systems, and usually have been implemented with operational amplifiers (op-amps). PID controller realizations using op-amps employ excessive number of active and passive components. Current conveyors, especially plus-type second-generation current conveyors (CCII+s) have larger bandwidth and dynamic range, and also greater linearity than op-amps (1). Employing only CCII+s simplifies the configuration thus gyrator (2), synthetic floating inductances (3-4), voltage- mode filter (5) and transfer function synthesis (6-7) employing only CCII+s have been reported in the literature. Despite of several circuits such as derivative, integral, proportion and summer constructed with op-amps (8-9) that can be used to implement PID, PI and PD controllers, current conveyors have not been used to realize PID, PD and PI controllers in the literature so far. In this paper, novel current-mode and voltage-mode PID, PI and PD controllers employing CCII+s as active elements are proposed. In the proposed current-mode controllers, output currents are taken from high impedance terminals of the CCII+s. Also input voltages are applied to the Y-terminals of the CCII+s in the presented voltage- mode PID, PI and PD controllers. These properties make the proposed circuit ideal for using in cascaded systems. All the proposed controller realizations employ only grounded passive components, and do not require passive element matching so the circuits are suitable for integration. The PID, PI and PD parameters can be selected independently. Also simulations are performed using SPICE program to verify the theoretical analyzes.

In this paper new simple Dual-input current-mode integrator/differentiator structures using differential voltage current conveyor (DVCC) are presented. The proposed circuits are composed of one DVCC and three passive components. The effects of the DVCC terminal tracking errors are analyzed, which shows that the time constants (tau) are practically active-insensitive. Compensation design equations are derived for correcting the value of tau that was altered due to the terminal tracking errors of the DVCC. The performances of the circuits are demonstrated on SPICE platform. IEEE Reg 8; IEEE Croatia Sect; Univ Zagreb, Fac Elect Engn Comp

A new realization of floating inductance and two R-L impedance simulators are presented, respectively employing three and two first generation current conveyors (CCI)s as active elements. All of the circuits use only plus type (CCI+)s and minimum number of passive elements. The circuits do not require component matching. The performances of the circuits are tested using SPICE simulation program.

In this paper new voltage-mode multifuction filters using operational transconductance amplifiers (OTAs) and internally compensated operational amplifiers (OP-AMPs) are presented. The first proposed voltage mode multifunction filter can realize highpass and bandpass responses and the second proposed voltage mode multifunction filter can realize bandpass, lowpass and bandstop responses simultaneously. No external passive elements are required thus the circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of the sensitivities are low. The performances of the circuits are tested using SPICE simulation program. IEEE; Tubitak; Istanbul Teknik Univ; Aselsan; Profile Telre; TURCom; Sgi; Datacore; Divit

In this paper, a new realisation of DVCC based current mode all-pass filter circuit is proposed. This circuit employs only one active element and three passive elements of which two are grounded. Using the proposed filter topology a new quadrature oscillator is presented as an application. SPICE simulations verify the theoretical results. IEEE; IEEE Circuits & Syst Soc; Univ Sharjah; Etisalat Coll Engn; Emirates Telecommun Corp; Amer Univ Sharjah; Thuraya Satellite Telecommun Co; Dubai Elect & Water Author

Phase equalizers also called all-pass filters are widely used to shift the phase of an analog signal without altering its magnitude. In this study, a new realization of phase equalizer using one current controlled conveyor (CCCII), one operational amplifier (op-amp) and two capacitors is presented. The proposed circuit does not use any resistors thus makes it suitable for integration. Also the pole frequency of the proposed circuit can be tuned electronically. Simulation results are included to verify theory.

In this paper, a new current-mode (CM) Kerwin-Huelsman-Newcomb (KHN) biquad is proposed. The proposed circuit employs three differential difference current conveyors (DVCCs) as active elements together with two capacitors and four resistors as passive elements, which all are grounded. The circuit simultaneously provides the three basic filter functions, namely bandpass (BP), highpass (HP) and lowpass (LP) functions. The output signals are obtained at high output impedance ports, which is important for easy cascading in current-mode operation. SPICE simulation results are given to verify the theoretical analysis. EURASIP; IEEE; IEEE French Chapter

Telif hakkı yayıncıya ait. In this paper a new trans-impedance mode multifunction filter using opamp compensation poles is presented. The proposed circuit is composed of two internally compensated operational amplifiers (OAs) and four single-output operational transconductance amplifiers (OTAs), without using any external passive elements. The proposed multifunction filter can realize lowpass, bandpass and highpass responses simultaneously. Lowpass and bandpass responses have low output impedances. No matching condition is required. The circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of the active sensitivities are low. The performance of the circuit is tested by using SPICE simulation program. IEEE

Telif hakkı yayıncıya ait. In this paper a new CMOS high performance dual-output realization of the third generation current conveyor (CCIII) is presented. The proposed CCIII provides good linearity, high output impedance at port Z and excellent input/output current gain. PSPICE simulation results using the MIETEC 1.2 μm CMOS process model are included to verify the expected values.

In this paper a new current-mode multifunction filter using opamp compensation poles is presented. The proposed circuit is composed of two internally compensated operational amplifiers (OAs) and five single output operational transconductance amplifiers (OTAs), without using external passive elements. The proposed multifunction filter can realize lowpass, bandpass, highpass and bandstop responses simultaneously all at high output impedances. The circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performances of the circuits are tested using SPICE simulation program. IEEE CAS Soc; Univ Zagreb, Fac Elect Engn & Comp; Portland State Univ, Elect & Comp Engn Dept; IEEE Reg 8; Croatian Acad Sci & Arts; Ericsson; IBM; HP Invent; Hrvatski Telekom; Croatia Airlines

In this paper a new configuration for the realization of first-order current-mode all-pass filters with high output impedance is presented. It can realize first-order allpass filtering function using two current controlled conveyors (CCCIIs) connected to four RC one-part elements. Eight different realizations for the proposed configuration are given in tabular form, which exhibit identical transfer functions but differ in the number of passive Components, component matching constraints possibility of electronically gain adjustment and other properties. PSPICE simulation results are given to confirm the theoretical analysis. IEEE; Agcy Natl Reglementat Telecommun; Minist Enseignenment Super Rech Sci; Secretatiat Etat Aupres Minist Enseignement Super Rech Sci Charge Rech Sci; SEPTI; CNRST; Rectorat Univ Mohammed V-Agdal; Sicotel; Silvaco Data Syst; STMicroelectr; Mentor Graph; Commune Agda/Ryad; Off Natl Eau Potable; Barid El Maghreb