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This paper presents design, mathematical analysis, and measurement of low noise single-stage transimpedance amplifier (TIA) with scalable bandwidth using 130 nm bipolar complementary metal-oxide-semiconductor (BiCMOS) silicon-germanium (SiGe) process. Common-emitter (CE) shunt-shunt feedback topology with active inductor peaking has been used in the design for improving noise, gain and driving capability of TIA by decreasing the input and output impedance, respectively. The use of active inductive peaking in CE shunt-shunt feedback topology has resulted in a new TIA configuration with better performance. The circuit has been optimized for low noise by adopting the proposed design technique. Validity of the mathematical analysis and design for the proposed TIA has been established with the help of simulations as well as measurement results. The measurement results of Ku-band TIA (10 MHz to 14 GHz) have demonstrated a transimpedance gain of $53.2~dB\Omega $ , input-referred current noise of 16.8 pA/ $\sqrt {Hz}$ with power consumption of $9.8~~mW $ . The design architecture is adaptable for higher frequency bands, which has been demonstrated by designing another TIA covering K- and Ka-bands (10 MHz to 35 GHz) with transimpedance gain of 33.4 dB $\Omega $ , input-referred current noise of 29.4 pA/ $\sqrt {Hz}$ with power consumption of $28.1~~mW $ in the post-layout simulation results, and occupies same chip area as that of 14 GHz, i.e., $0.1\times 0.21\,\,mm^{2}$

In high dose per pulse charged particle beams, all online detectors saturate due to ion recombination. It is therefore impossible to count detector pulses separately. Silicon carbide due to its high bandgap, high thermal conductivity, and high displacement energy, is seen as an alternative. Analyzing waveforms in real-time is challenging in terms of bandwidth, measurable energy range, sensor size, data rate. In this context, an Analog Front-End (AFE) was designed for radiation signal processing. It is based on a Transimpedance Amplifier (TIA) and Charge Sensitive Amplifier (CSA) respectively, to analyze the shape of the generated signal. The methodology used to characterize AFE for large detector capacitance is described. The results obtained from simulations, experiments, and measurements in a radiative environment are also presented. [ABSTRACT FROM AUTHOR]

Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with- $2.5~\mu \text{A}_{\mathrm {rms}}$ input-referred noise. Optical measurement results at 100 Gb/s show that −8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a front-end integrated circuit for ultrasound (US) harmonic imaging, interfacing to a one-dimensional capacitive micromachined ultrasonic transducer (CMUT). It contains a complete ultrasound receiving chain, from analog front-end (AFE) to gigabit/s data link. A two-stage self-biased inverter-based transimpedance amplifier (TIA) is proposed in this work to improve tradeoffs between power, noise, and linearity at the first stage. To improve harmonic imaging performance, the design is further equipped with a 4 $^\text {th}$ -order highly programmable bandpass filter, which has a tunable bandwidth from 2 MHz to 15 MHz. An 8 b 80 MS/s SAR ADC digitizes the signal, which is further encoded and serialized into an LVDS data link, enabling a reduction in the number of output cables for future systems with multiple ADCs. The design is realized in a 40 nm CMOS technology. Electrical measurements show it consumes 2.9 mW for the AFE and 2.1 mW for the ADC and digital blocks. Its overall dynamic range varies from 61 dB to 69 dB, depending on the reception bandwidth. The imaging capability of this design is further demonstrated in a US transmission and reception imaging system. The acoustic measurements prove successful ultrasound harmonic acquisition, where the on-chip bandpass filter can improve the lateral resolution by more than 30%. [ABSTRACT FROM AUTHOR]

This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in TSMC 40-nm CMOS process. The system consists of a differential 100-Ω termination, a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. The source-degenerated transconductance stage and inverter-based transimpedance (TIA) with source follower structure are adopted for both CTLE and VGA. The utilization of source follower can solve the harsh DC operation problem in conventional inverter-based TIA and extend the bandwidth. By altering the source-degenerated resistors and capacitors in the two-stage CTLE, the proposed AFE can reach fixed peaking frequency with 9-dB compensation range at high frequency. Moreover, it can also achieve a fixed bandwidth at 14 GHz and 9.5-dB DC gain tuning range when altering the feedback resistors and negative capacitance compensation network (NCC) in VGA. Measurement results demonstrate that: it can compensate for 7.3-dB channel loss at 14-GHz Nyquist frequency and open the closed eye for 56-Gb/s PAM4 signal with BER < 10−8 from 215 – 1 PRBS input. The core of the AFE occupies 0.32-mm2 area and consumes 30-mW power from 1.1/1.2-V supply. [ABSTRACT FROM AUTHOR]

Analog front-end (AFE) circuits with wide dynamic range and low walk error for cost-effective phase-shift LADAR receiver are presented in this work. The inverter-based trans-impedance amplifier (TIA) utilized in the proposed AFE has been modified with two additional transistors in its input node, which can attenuate the input current automatically and adjust the bandwidth dynamically. The improved TIA significantly increases the dynamic range of AFE without any complicated gain-control circuits, while keeping the walk error in a low level. Heterodyne techniques are then adopted to modulate the received signals to low-frequency carriers, as well as the driving signal of laser diode, which is modulated with a mirrored voltage-input channel. Thus, systematic errors caused by the uncertainty of the initial phase in transmitted signal can be reduced. As a result, high-accuracy phase detections and range measurements can be realized conveniently by just sampling two low-frequency (~100 kHz in this design) output signals. The AFE circuits have been fabricated in a standard 65-nm CMOS technology with a total chip area of $0.59\times0.68$ mm2 including the IO PADs. The measured power consumption is 24.3 mW with a 2.5-V supply. With a modulated frequency of 30 MHz and a local oscillator frequency of 30.1 MHz, the measured input-referred noise of the proposed AFE is 8.4 nA $_{RMS}$ and the walk error is less than ±1.8% for a wide dynamic range of 500 nA ~ 10 mA. The measurement results show that the proposed AFE can achieve wide dynamic range and low walk error, while the system complexity and cost of the phase-shift LADAR receiver can also be reduced. [ABSTRACT FROM AUTHOR]

This article presents a current mode transimpedance amplifier (TIA) implemented in a standard 65-nm CMOS technology for the applications of elder-care home monitoring LiDAR sensors. Particularly, a novel mirrored current–conveyor (MCC) input configuration is proposed to lower the input impedance, thus achieving a wide bandwidth. This MCC-TIA can alleviate severe pulse spreading issue for near-range detection, enabling effective narrow-pulse recovery. Also, a feedforward control-voltage generator is newly suggested to realize an automatic gain-control within a single pulse-width duration. Measured results demonstrate the variable transimpedance gain of 59~77 dB $\Omega $ to accommodate the incoming input currents of $18~\mu \text{A}_{pp} \sim ~2.24$ mA $_{pp}$ that corresponds to the feasible detection range of 0.5~5.3 meters in an elder’s home. The bandwidth of 83 MHz~2.6 GHz is measured with the minimum noise current spectral density of 16.8 pA/sqrt(Hz). The chip dissipates 40 mW in total, and occupies the area of 1.0 mm2, including I/O pads. [ABSTRACT FROM AUTHOR]

This brief presents a 2.4 GHz receiver front end in the form of architecture of quadrature LNA-Mixer-VCO-filter (QLMVF) cell in 180 nm CMOS with split-transconductance amplifiers (TCAs). Instead of a single stack-current-reusing QLMV scheme, the proposed design employs two separate current reuse stages with a passive mixer to provide better flicker noise and linearity performance. A shunt-inductive input-match single-ended low noise amplifier (LNA) proposed with an improved package parasitic compensation through a simple varactor tuning. The quad-flat-no-leads (QFN) packaged receiver provides a measured maximum conversion gain of 40 dB, a noise figure (NF) of 10 dB, and a third-order input intercept point (IIP3) of −5 dBm with a spurious-free dynamic range (SFDR) of 60 dB. The front end consuming 2.7 mW of power from a 1.8 V supply and occupies an area of 1.5 mm2. [ABSTRACT FROM AUTHOR]

This letter presents the design and measurements of a monolithically integrated photonic receiver manufactured in 0.25 $\mu \text{m}$ SiGe BiCMOS electro-photonic technology. The receiver consists of an on-chip germanium photodiode directly connected to the transimpedance amplifier (TIA). An on-chip, low-noise feedback loop compensates the dc photocurrent. The circuit provides a maximum bandwidth of 35.6 GHz at a gain of 59.2 dB $\Omega $ with a noise of 12.34 pA/ $\sqrt {\text {Hz}}$ while consuming only 80 mW. In combination with a 20 GHz, 1550 nm electro-optical transmitter, a maximum data rate of 50 Gb/s at a bit error rate of less than $10^{-{12}}$ was measured. To the best of the authors’ knowledge, this is the fastest error-free detected data rate reported for a monolithically integrated photonic receiver. Additionally, the feedback resistor of the TIA can be tuned via a MOSFET allowing error-free operation at 20 Gb/s with a sensitivity of only −13 dBm. In this setting the input-referred noise is only 8.16 pA/ $\sqrt {\text {Hz}}$. [ABSTRACT FROM AUTHOR]

The design methodology and circuit implementation of a transimpedance (TI) amplifier (TIA) featuring low averaged input-referred current noise density without compromising the TIA bandwidth (BW) are presented. The technology role in the key performance metrics is also discussed and verified by means of two analogous TIA designs implemented in two different 130-nm SiGe:C BiCMOS processes from IHP, SG13S with fT/f\max = 250/340 GHz and SG13G2 with fT/f\max = 300/500 GHz. Both TIAs adopt a fully differential linear architecture with three stages: an input shunt-feedback TI stage followed by a variable gain amplifier which provides post-amplification with 15-dB gain control range and an output 50- \Omega buffer. The TIA in SG13S features 68.5 dB \Omega differential TI gain, 42-GHz 3-dB BW, and 8 pA/ \sqrt \mathrm Hz averaged input-referred current noise density while the second TIA in SG13G2 provides 65 dB \Omega differential TI gain, 66-GHz 3-dB BW, and 7.6 pA/ \sqrt \mathrm Hz . Measured total harmonic distortion in both TIAs in the maximum gain condition is better than 5% for ~800 mVppd output swing and input currents of ~300 $\mu $ App. Both circuits dissipate 150 mW of power and are shown to operate at up to 100 Gb/s data rate with clean PRBS31 non-return to zero and PAM-4 eye diagrams. To the author’s best knowledge, the reported TIAs exhibit the lowest averaged input-referred current noise density shown to date at a BW sufficient to support 100 Gb/s net data rate, surpassing other silicon-based and InP implementations toward the next-generation 400 Gb/s optical links. [ABSTRACT FROM PUBLISHER]

Optical interconnects are being increasingly deployed in data centers to meet growing bandwidth requirements under tight power constraints. Therefore, there has been renewed focus on increasing data rates and improving power efficiency of optical links. Among all the link components, laser diodes typically consume the most power. Their power dissipation is dictated by the amount of signal power that needs to be transmitted to meet the bit error rate requirements under given channel loss and receiver sensitivity conditions. Consequently, improving receiver sensitivity directly helps lowering laser diode power consumption. In this paper, we present design techniques to implement such high sensitivity optical receivers. To this end, we identify noise–bandwidth tradeoffs of a shunt feedback transimpedance amplifier (SF-TIA) and elucidate how they limit the maximum achievable sensitivity at a given data rate and process technology. We then propose to combine a low-bandwidth SF-TIA with a four-tap decision feedback equalizer to overcome this noise–bandwidth tradeoff. The proposed SF-TIA uses high-gain multistage amplifier and large feedback resistance and achieves greatly improved noise performance. Fabricated in a 65-nm CMOS technology and heterogeneously integrated with a photonic IC, the proposed optical receiver achieves optical modulation amplitude sensitivity of −16.8 dBm with 1.9-pJ/bit efficiency at 12 Gb/s. [ABSTRACT FROM AUTHOR]

A scannerless laser detection and ranging (LADAR) system based on frequency modulation/continuous wave (FM/cw) technique is attractive due to a reduced bandwidth requirement of the receiver circuit. This paper presents the 64\times 64 InGaAs-based focal plane array (FPA) self-mixing detectors and the 1\times 32 element readout integrated circuit (ROIC) array based on transimpedance amplifier for the FM/cw LADAR. Different from conventional detector, the InGaAs self-mixing detector presents a low impedance and a complex electrical model. The linear chirp local-oscillator (LO) electrical signal through the detector causes a large dc current and a unique dc offset voltage (Vos) error in the ROIC. To overcome these problems, the blocking capacitors and the novel multiple low-pass filters are applied in the ROIC. The ROIC array was fabricated in 0.18- \mu \textm CMOS process. The measured results show that the Vos error is eliminated within the limited LO amplitude range and the ROIC achieves a 140-dB \Omega transimpedance gain with a bandwidth of 1 MHz. Compared with the state-of-the-art FM/cw LADAR, the ROIC accurately detects the signal of interest of the InGaAs FPA self-mixing detectors and miniaturizes the LADAR receiver. [ABSTRACT FROM PUBLISHER]

CMOS capacitive micromachined ultrasonic transducer (CMUT) with integrated front-end circuits for portable high resolution ultrasonic imaging systems is presented. The CMUT array operates with 30 V power supply. In addition, the interlayer metal CMUTs with non-uniform membrane are proposed to improve the sensitivity in this paper. A prototype chip containing 48 elements as 12 channels is implemented. The conversion efficiency of the proposed CMUTs is 5.84 times higher than that in the published literatures. The maximum ultrasonic signal bandwidth is 4.5 MHz. CMUT array and the transimpedance amplifiers are integrated on the same chip. In addition, a multibit continuous-time $\Delta \Sigma $ modulator was designed and fabricated in another chip using 0.18- \mu \text{m} standard CMOS process. The chips size are 1.84 and 0.177 mm2, and the total power consumption in the receiving mode is approximately 3.01 mW with 1.8 V power supply. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel efficient method for the design of high-gain resonant transimpedance amplifiers (TIAs) using MATLAB. The procedure provides the designer with an effective tool, useful to explore the effects of different device parameter combinations in complex network topologies used in several application fields. We applied this method to improve the detection capability of a previously designed chlorophyll-A (Chl-A) sensor, in order to in-vivo assess the seawater quality. By exploiting the interesting bandpass behavior exhibited by a T feedback network, we were able to redesign the resonant TIA stage of a low-cost lock-in amplifier working at 1 kHz, easily increasing the gain by a factor of 100, and reaching an overall gain of 216 dB while reducing the detectivity to almost 500 fA. Moreover, the proposed analysis provides the optimal circuit parameter values for a wide working frequency range without further numerical optimization, giving an interesting perspective of its potential use in those telecommunication applications where high sensitivity is required. [ABSTRACT FROM PUBLISHER]

A variable-gain current-amplifier-based feedback transimpedance amplifier (CA-TIA) with a gain-insensitive bandwidth is analyzed and designed for gigabit-per-second optical wireless communications. Implemented in 0.18- \mu\textm CMOS, as the transimpedance gain varies from 55.8 to 69.3 \textdB\Omega, the 3-dB bandwidth of the CA-TIA remains relatively invariable around 1 GHz. [ABSTRACT FROM AUTHOR]

We design a low-noise, large-dynamic-range amplifier based on transimpedance amplifier (TIA) for detecting shot noise of 1064-nm laser in quantum optical experiments. Compared with a single-junction field-effect transistor (JFET) buffered TIA, the electronic noise is effectively 2.8 dB suppressed at the analysis of 2 MHz, and 4 dB suppressed at 4 MHz by means of a JFET bootstrap structure. Under the transimpedance gain of 200 kΩ and 0.5 pF, the measured shot noise at the injected laser power of 51 μW is 12.5 dB above the electronic noise at 2 MHz, and 9.8 dB at 4 MHz. With adjustment of bias condition of the bootstrap structure and application of a L-C (inductance and capacitance) structure, the dynamic range is largely boosted from the original 1.52 to 11.22 mW. The amplifier meets the requirement of SNR for Bell-state detection in quantum optical experiments. [ABSTRACT FROM AUTHOR]

To address the two main challenges concerning the design of a transimpedance amplifier (TIA), namely, improving the sensitivity of the TIA without sacrificing bandwidth and suppressing inter-symbol interference (ISI) due to insertion loss, a 25 Gb/s optical receiver (RX) based on 65 nm CMOS technology, including a TIA and a PD operating at 1.3 \mu\m wavelength, was developed. The key components of the TIA are a two-stage offset-cancelation scheme and a low-voltage output driver with peaking gain of 7.7 dB at 12.5 GHz. This driver performance is achieved by separating the equalizer function and output buffer of the driver. The TIA attains a sensitivity of -9.7 dBm (86-\mu\\rm App) OMA and an eye opening of 65% at data rate of 25 Gb/s. The optical RX operates at 28 Gb/s with sensitivity of -8.2 dBm (121-\mu\\rm App) OMA. Utilizing the CMOS TIA, an implemented VCSEL-based optical link operating at 850 nm wavelength achieves sensitivity of -7.3 dBm (98-\mu\\rm App) OMA. Power consumption and power efficiency of the optical RX at data rate of 28 Gb/s are respectively 137.5 mW and 4.9 mW/Gb/s. [ABSTRACT FROM AUTHOR]

A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that improves resilience against possible laser diode (LD) failure. To alleviate degradation of the optical link due to power-supply variations, a power-supply-noise-tolerant 25-Gb/s analog FE (consisting of a TIA with a noise canceller and a fully differential LD driver) is proposed. The noise canceller can keep the power-supply variation below 0.2 mV at frequencies down to 1 MHz, and the fully differential LD driver can keep power-supply current variation below 0.64 mApp/ch, despite a large modulation current of 20 mApp. As for the transmission performance of the transceiver, eye diagrams experimentally confirmed 25-Gb/s and 6.25-Gb/s data-transmission rates. A 25-Gb/s optical-link test on the transceiver demonstrated error-free operation at –6.1-dBm OMA. Moreover, an image-transfer test on the transceiver operating at a data rate of 20 Gb/s through a 100-m multi-mode fiber was demonstrated. Total power consumption of the transceiver (including optics) was 2.2 W at full-channel operation. [ABSTRACT FROM PUBLISHER]

A fully integrated near-infrared spectroscopy photoreceiver including two new silicon avalanche photodiodes (SiAPDs) and a new transimpedance amplifier (TIA) is proposed in this paper. SiAPDs are designed in p+/n-well structure with guard-rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise, low-power consumption, high gain-bandwidth product characteristics and it is robust against power-supply variation (1-3 V). This circuit is developed using 0.35 μm CMOS technology and the measurement results are compared with other results from the literature. The designed rectangular and octagonal SiAPDs have the avalanche gain of 100 and 45 with the breakdown voltage of 9 and 6 V and the photon absorption efficiency of 45% and 25% at 800 nm. Fabricated TIA offers high-transimpedance gain (up to 250 MV/A), tunable BW (1 kHz-1 GHz), extremely low input and output noises (100 fA/√Hz, 1.8 μV/√Hz), and low-power consumption (0.8 mW). The impact and effects of on-chip integration of SiAPD and TIA front-end have been also measured and evaluated. [ABSTRACT FROM PUBLISHER]

This paper describes the design of a multi-gigabit fiber-optic receiver with integrated large-area photo detectors for plastic optical fiber applications. An integrated 250 \mu\m diameter non-SML NW/P-sub photo detector is adopted to allow efficient light coupling. The theory of applying a fully-differential pre-amplifier with a single-ended photo current is also examined and a super-Gm transimpedance amplifier has been proposed to drive a C PD of 14 pF to multi-gigahertz frequency. Both differential and common-mode operations of the proposed super-Gm transimpedance amplifier have been analyzed and a differential noise analysis is performed. A digitally-controlled linear equalizer is proposed to produce a slow-rising-slope frequency response to compensate for the photo detector up to 3 GHz. The proposed POF receiver consists of an illuminated signal photo detector, a shielded dummy photo detector, a super-Gm transimpedance amplifier, a variable-gain amplifier, a linear equalizer, a post amplifier, and an output driver. A test chip is fabricated in TSMC's 65 nm low-power CMOS process, and it consumes 50 mW of DC power (excluding the output driver) from a single 1.2 V supply. A bit-error rate of less than 10 ^-12 has been measured at a data rate of 3.125 Gbps with a 670 nm VCSEL-based electro-optical transmitter. [ABSTRACT FROM AUTHOR]

A 1.25-Gb/s burst-mode receiver for the application of 32 splits and 20-km transmission in Ethernet-based passive optical network was developed using a general planar type avalanche breakdown photodiode and a low-cost continuous-mode transimpedance amplifier (TIA). The largest loud/soft ratio (27.3 dB) and high sensitivity (-33.3 dBm) were achieved in 896-ns guard band. The minimum automatic gain control (AGC) time of the TIA was obtained without using a high value external AGC capacitor that is needed for the stable continuous operation. The guard time could be minimized while maintaining the burst performances due to the fast laser on-off time of the optical network units. [ABSTRACT FROM PUBLISHER]

Today's wireless core network is based on a circuit-switched SS7 architecture similar to that found in wireline telecommunications networks. With the advent of IP technologies and the tremendous growth in data traffic, the wireless industry is evolving its core networks toward IP technology. Wireless telecommunications started as an offshoot of wireline telephony, and the absence of global standards resulted in regional standardization. Two major mobile telecommunications standards have dominated the global wireless market, namely, TDMA/CDMA developed by the TIA in North America and GSM developed by the ETSI in Europe. As we move toward third-generation wireless, there is a need to develop standards which are more global and collaborative. The global wireless industry has created two new global partnership projects, SGPP and 3GPP2, to address the issue of the limited data capabilities of 2G systems, motivating the partnership projects (PPs) to start work on 3G wideband radio technologies that can provide higher data rates. This work resulted in 3G wireless radio technologies that will provide data rates of 144 kb/s for vehicular, 384 kb/s for pedestrian, and 2 Mb/s for indoor environments, and meet the ITU IMT-2000 requirements. Now that the radio technology standards to support higher data rates have been developed, the PPs are focusing on development of standards for all-IP networks. We discuss the genesis of 3GPP and 3GPP2 IP work, outlining the important architectural differences of the two groups. Currently, 3GPP and 3GPP2 offer divergent proposals that need to be harmonized if convergence toward an IP-based mobile telecommunications networks is to become a reality [ABSTRACT FROM PUBLISHER]

Machine-to-machine (M2M) communications are gaining more prominence in wireless communication. However, the current systems are optimized more for human-to-human (H2H) than M2M communications. Therefore it's important that wireless technologies evolve and develop competitive capabilities to efficiently support M2M communications. This article presents a snapshot of the progress made in developing M2M communication standards. [ABSTRACT FROM PUBLISHER]