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In this letter, a high-power microwave (HPM) hardened structure for a split-gate enhanced power U-shaped trench-gate metal–oxide–semiconductor (SGE-UMOS) field-effect transistor is proposed. Also, a mathematical model of HPM induced voltage is established. Compared with the standard SGE-UMOS structure, the radiation immunity of the proposed structure has been improved by a value exceeding 200, with burnout time improving from 120 ns to 27.76~\mu \texts . Additionally, a detailed investigation is carried out by a 2-D numerical mixed mode simulation via ATLAS to optimize the HPM hardened SGE-UMOS structure. The simulation results demonstrate that a 106% improvement in the figure of merit (including the breakdown voltage and ON-resistance) is achieved in the optimized structure. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of the single-event burnout (SEB) in the floating field ring (FFR) termination of a power MOSFET for the first time. We investigate the SEB triggering mechanism and SEB performance based on a 140-V typical FFR termination, and find that the structure is sensitive to SEB because of a sharp temperature rise appearing at the p+ base/n-drift junction. A 140-V hardened FFR termination (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also studied in this paper that can demonstrate much better SEB performance without sacrificing the basic characteristics compared to the standard one. In addition, the hardening mechanism is explained, and the performances of the hardened structures with different buffer layer thickness are discussed. As a result, the safe operating area can reach the value of the breakdown voltage when the thickness achieves or exceeds 3~\mu \textm . [ABSTRACT FROM AUTHOR]

A 60-GHz 4-bit vector-summing phase shifter has been implemented in a 90-nm CMOS process. Based on a tunable current-splitting technique with $\pi $ -type low-pass filter (LPF) and T-type high-pass filter (HPF), a quadrature adjustable amplitude generator is developed to improve the insertion loss and adjust quadrature signals’ amplitudes. Variable gain amplifiers (VGAs) that are widely used in traditional phase shifters are replaced by the generator to reduce power consumption. In addition, a balun-based current-reuse technique is applied to further save dc power. The overall consumed direct current is 11 mA under 1.8-V voltage supply. The measured results show that the phase shifter with an output balun (with loss of 1.6 dB) achieves gain of $-{{0.4}}{\sim }{{2.5}}~{\text {dB}}$ at 60 GHz and root mean square (rms) gain error is ${{0.75}}{\sim }{{1.6}}~{\text {dB}}$ in the frequency regime from 57 to 64 GHz. The peak average gain is 1.1 dB at 59.7 GHz. By employing a calibration method, the measured rms phase error ranges from 2.3° to 7.6° from 57 to 64 GHz. The tested 60-GHz input 1-dB compression point (P_{1\mathrm {dB}}) and noise figure (NF) for 16 phase states are −9.8 ± 0.8 dBm and 11 ± 1.3 dB, respectively. [ABSTRACT FROM PUBLISHER]

A lumped-element model for ON-chip interconnects is proposed in this paper. The effect of current return path of interconnects is analyzed. An efficient analytical parameter extraction method for the model is proposed. The inductor Lg was adopted in the shunt branch of this model to characterize the induced time-varying magnetic field. Thus, the bandwidth of the model is extended over the resonance frequency. A group of interconnects with different structures were fabricated in a 0.18- \mu \textm CMOS process to investigate the effects of current return path. The good agreement of $S$ -parameters between the model and measurements suggests that the proposed model can accurately predict the performance of interconnect in a wide frequency band up to 80 GHz, even over the resonance frequency. [ABSTRACT FROM PUBLISHER]

A bandwidth enhanced method of a low-profile substrate integrated waveguide (SIW) cavity-backed slot antenna is presented in this paper. Bandwidth enhancement is achieved by simultaneously exciting two hybrid modes in the SIW-backed cavity and merging them within the required frequency range. These two hybrid modes, whose dominant fields are located in different half parts of the SIW cavity, are two different combinations of the TE110 and TE120 resonances. This design method has been validated by experiments. Compared with those of a previously presented SIW cavity-backed slot antenna, fractional impedance bandwidth of the proposed antenna is enhanced from 1.4% to 6.3%, its gain and radiation efficiency are also slightly improved to 6.0 dBi and 90%, and its SIW cavity size is reduced about 30%. The proposed antenna exhibits low cross polarization level and high front to back ratio. It still retains advantages of low-profile, low fabrication cost, and easy integration with planar circuits. [ABSTRACT FROM AUTHOR]