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A time-and-frequency hybrid multiplexing technique for a multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) radar is proposed. Discrete Fourier transform (DFT)-coded OFDM waveforms are introduced, which allow it to be free from range-dependent angle errors. These are readily used to provide both time-domain multiplexing and frequency-domain multiplexing in the MIMO OFDM radar. The DFT- coded frequency-domain multiplexing shortens the maximum unambiguous range, while the DFT- coded time-domain multiplexing lowers the maximum Doppler ambiguity. A hybrid of both domain multiplexing techniques can mitigate the respective limitations by adaptively selecting the proper DFT matrix size in each multiplexing domain. This allows to solve the intrinsic range and Doppler ambiguity problems of MIMO radars by controlling the hybrid ratio of the two kinds of DFT- code based multiplexing methods. Range-Doppler and range-angle maps of four examples with different hybrid multiplexing ratios are simulated with a MIMO OFDM radar numerical platform.

A 28-GHz power amplifier (PA) with adaptive cross feedback (ACF) is presented. The ACF is employed by an adaptively controllable RC-feedback circuit from the source to the opposite drain nodes of the common-gate (CG) stages in a differential cascode amplifier. The proposed ACF makes the PA stable even with large power transistors. It also linearizes the PA by decreasing the feedback adaptively at high powers which improves amplitude distortion (AM-AM) and power-added efficiency (PAE) as well as the saturation power (P Sat ). The proposed PA is implemented with a 28-nm bulk CMOS process with a 0.144 um2core chip area. It is shown that the ACF increases P Sat , peak PAE, and output 1-dB gain compression point (OP 1dB ) from 20.1 dBm to 20.4 dBm, 34% to 37.2%, and 17.4 dBm to 18.2 dBm, respectively at 28.5 GHz. The proposed PA shows a 28-dB peak gain at 28.6 GHz with 26.8 GHz to 30.8 GHz (14.0%) 3-dB gain bandwidth, which is the highest P Sat and gain among the reported Ka-band bulk CMOS PAs.

A frequency reconfigurable dual-band power amplifier (PA) with reconfigurable transmission line transformers (TLT) is presented, which can be operated at both the n257 (26.5-29.5 GHz) and n260 (37–40 GHz) 5G communication bands. The PA utilizes reconfigurable TLTs for output and input matching networks to reconfigure the PA between the n257 and n260 bands with optimal performance in both bands. The reconfigurable TLTs provide frequency reconfigurability to the PA by changing both the primary and secondary side inductances of the TLTs. The switches for the TLTs are located in the space inside the TLTs, which results in a small overall chip area. The dual-band PA is fabricated using a 28-nm bulk CMOS process. It achieves 20.2 and 19.1 dBm saturated output powers, 18.7 and 18.6 dBm 1-dB compressed output powers and 33.6% and 32% peak power added efficiencies at 26.5 and 37 GHz, respectively. The dual-band PA has a core size of 0.11 mm2.

A differential four-way power divider in 65 nm CMOS process for a beamforming front-end IC is presented, which provides stable virtual grounds regardless of grounding inductance variations. The chip size is reduced by using a 4-way Wilkinson power divider based on lumped elements. It has a small core chip size of 0.09 mm’. At 24 to 30 GHz, it has a low insertion loss of only 0.93 to 1.94 dB, a port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has small amplitude and phase difference which are much better than a single-ended structure.

In this paper, on-chip de-embedding methods are compared by applying to transistor characterization for up to 110-GHz. 2-step and 3-step methods, based on lumped circuit models, and hybrid methods, which are a combination of a cascade model and the lumped circuit model, are studied. For cascade models of the hybrid methods, two sets of de-embedding structures are adopted - (LINE, PAD-LINE) and (THRU LR, THRU LLR) are used for the hybrid-1 method and hybrid-2 method, respectively. A single transistor is used as a device under test (DUT) and all de-embedding patterns for the four methods are implemented with 28-nm fully depleted silicon on insulator (FDSOI) process. Transistor characteristics including gate resistance and parasitic capacitances of FDSOI MOSFETs are extracted and analyzed. In addition, ft and f max of the device are estimated by using the hybrid-1 method.

This paper proposes a Ka-band 5-bit switched dual-side microstrip line true-time-delay phase shifter in 28 nm bulk CMOS process. The dual-side microstrip line has vertical arrangements of delay lines and reference lines, which allow implementing compact switched-line phase shifter. The delay cells are implemented with lumped elements which are miniaturized with low self-resonance-frequency inductors. These are very small but have many parasitic capacitances of which resonances are used to make time delays. With these techniques, the proposed TTD phase shifter controls 36.9 ps with the core area of 0.07 mm2. This is the smallest size among the reported Ka-band TTD phase shifters.

A differential-phase radar with amplitude-compensated complex signal demodulation (ACCSD) is presented., which can detect vital-signals from one-side of the human body even during back-and-forth random movements. Differential signal demodulation is achieved using the proposed ACCSD method. Compared with the conventional complex signal demodulation (CSD) method, the proposed method can avoid a distortion due to amplitude variations of baseband signal. Experiments also show that the proposed ACCSD provides the results identical to those of an extended differentiate and cross-multiply (DACM) method, while the processing time of the ACCSD is 10 times faster than that of the extended DACM.

A highly efficient 94-GHz push-push frequency doubler is presented. The push-push frequency doubler is implemented with a commercial 65-nm CMOS process and can be operated in high-power mode (HPM) and high-efficiency mode (HEM). In HPM, it shows peak conversion gain of 1.94 dB, operating in the frequency range from 83.6 to 102.9 GHz (20.7%) with the input power of -1 dBm within 3-dB gain variation. Also at 94 GHz, it operates in the input power range of −11.9 to 8 dBm within 3-dB gain variation. In HEM, the peak total efficiency (P OUT /(P DC + P IN )) is 16.28%, which is the highest among those of the reported W-Band frequency doublers.

A wideband W-band 6-bit vector-sum based active phase shifter which was implemented using a 28-nm RF CMOS process is presented. The proposed phase shifter consists of a differential I/Q generator and a vector-summing amplifier with differential input and output buffers to use virtual grounds at high frequencies. The I/Q generator was designed with a differential hybrid coupler structure, and the mismatch in its differential input should be small to obtain accurate I/Q signals. To reduce the differential mismatch at the I/Q generator input, source cross-coupling capacitors are introduced at the common-gate stage of the cascode input buffer. The measured results indicate a root mean square (RMS) gain error of 0.69-0.98 dB and RMS phase error of 6.8-9.3 degrees over a wide frequency range of 76 GHz to 104 GHz. The average peak gain of all 64 states is 3.5 dB at 82 GHz. The fabricated phase shifter has a chip area of 0.32 mm2 with power consumption of 26 mW.

Millimeter-wave beamforming front-end ICs have been studied intensively as the service of 5G wireless communication is scheduled to begin in the near future [1–4]. The ICs include circuit elements such as PAs, LNAs, phase shifters, variable gain blocks, and switches to support antenna arrays for RF/hybrid beamforming. Due to the large number of antennas required for beamforming, the beamforming IC should include as many circuit elements as possible in a chip. The IC also needs high phase- and gain-control resolutions not only for controlling the beams precisely but also for error corrections and calibrations [1]. However, higher-bit controls of the phase and gain as well as high transmitting power increase the chip size in conventional structures, posing a trade-off between them. The front-end IC structure proposed here increases both transmitting power and gain/phase resolutions without increasing either the chip size or the power consumption.

A 24 GHz frequency modulated continuous wave radar system to recognize human's hand gestures is implemented, which uses commercial off-the-shelf RF front-end IC with one transmitter and four receivers. Planar patch array antennas, signal conditioning circuits and interconnections to a PC are designed for the system. Range-Doppler maps for four receiver channels are obtained with saw-tooth chirping signals transmitted to detect hand gestures. The radar system shows real-time highly accurate gesture recognition. Long-short term memory recurrent neural network as a supervised machine learning technique is used. Seven kinds of hand gestures are recognized within 0.4 m and $\pm 30^{\text{o}}$ from the center of the transmitted antenna with above 91 % accuracy.

In this paper, low-loss and small-size single-pole double-throw (SPDT) switches using a switched inductor are presented. The switched inductor is composed of a single inductor and two inductor switches which reconfigure the inductor between two output ports. It is designed to be connected to a turned-off series FET switch to resonate out the off-capacitance. All ports are matched to 50 Ohm by using the single inductor, which allows it to have low insertion loss (IL) and small size. Two types of SPDT switches which have the switched inductor are implemented in 65 nm CMOS process, one is a series type switch and the other is series-shunt type one. The series type one shows 0.89 dB IL, 18.2 dB isolation and the input P1dB of 12.55 dBm at 28 GHz, whereas the series-shunt type one shows 1.06 dB IL, 39 dB isolation and the input P1dB of 7.25 dBm. Both SPDT switches are operated in 25–39.5 GHz maintaining return loss less than −20 dB. Size of series and series-shunt type of the SPDT switches are 0.009 mm2 and 0.01 mm2, respectively.

A ring resonator sensor platform to measure humidity and CO 2 gas concentrations is presented which operates at 10GHz. The magnitude and frequency of the resonance are very sensitive to surrounding materials. The sensor can measure humidity and CO 2 gas concentrations by placing proper adsorption materials on the resonator. The sensor consists of an adsorption materials, coplanar waveguide (CPW) transmission lines and a ring resonator fabricated on PCB (TLY-5A). A specific adsorption paper is attached to the ring resonator for detecting a specific gas. We use a CoCl 2 based paper for sensing humidity and a dichlorophenolindophenol (DIP) based paper for sensing carbon-dioxide (CO 2 ) gas. The concentrations are found by analyzing variations of the resonance peak frequency and magnitude.

24GHz pulsed Doppler radar transmitter is presented, which is implemented with 0.13 um CMOS process. The transmitter include VCO, VCO buffer, Tx buffer and power amplifier, which produce pulses of very small duty with low power consumption. The measured transmitter phase noise of the VCO is −103 dBc/Hz, and the tuning range is 24 ∼ 25.4 GHz. The CW output power of power amplifier 10 dBm with 22% PAE. Implemented transmitter chip size was 1.06 mm × 0.98 mm.

In this paper, a 60 GHz transformer based wide noise figure (NF) bandwidth low noise amplifier (LNA) is presented. The proposed LNA consists of 2-stage cascode differential structure with transformer in each matching network. It is implemented with Clover-shaped transformer to get wide band performance of the NF and proposed Pot-shaped transformer to achieve low loss and area effectiveness. This shows the NF of 5.16 dB, and the variation of the NF in gain bandwidth is less than 0.4 dB. Gain and bandwidth of the LNA is 20.2 dB and 5 GHz with 28 mW DC power consumption. Also, the gain variation of the proposed LNA is 7 dB to 20.2 dB. This is fabricated using 65-nm RF CMOS process with a chip area of 0.54 × 0.8 mm2.

A 2-stage 1.7-GHz Doherty power amplifier (PA) with an adaptive bias (ADB) circuit was designed for small-cell base station applications. An uneven power cell size ratio was used to provide a large back-off efficiency for high peak-to-average power ratio (PAPR) signals. To simplify the power divider and inter-stage matching network, a lumped Lange-type quadrature coupler was used. The leakage signal from the isolated port of the coupler was used as an input signal for the ADB circuit of the peaking amplifier. The PA was implemented in a 0.25-μm GaN on a SiC MMIC process. For a 1.7-GHz continuous wave, the PA has a 45.8% power added efficiency (PAE) at the output power of 38.6-dBm and a 31.2% PAE at 7-dB back-off power. For an LTE downlink signal, adjacent channel leakage ratio (ACLR) of −25.9-dBc was obtained at the average output power of 31.4-dBm without a digital pre-distortion (DPD).

This paper reports a unique 4-terminal MEMS relay (actuation is electrically isolated with signal passage) employing a novel one-contact design to overcome high contact resistance problem of the conventional 4-terminal MEMS relay which utilizes a typical two-contact design. The fabricated 4-terminal MEMS relay with the one-contact design demonstrated a contact resistance of 18 mΩ, which is two order-of-magnitude lower value than that of the conventional two-contact design. To the best of our knowledge, this result is the lowest value in the 4-terminal MEMS relay and comparable value with the state-of-the-art in 3-terminal MEMS relay [14]. In addition, the relay was operated up to 1.1 × 106 cycles at 1 V / 50 mA in an air and hot switching condition with negligible contact resistance variation. The lifetime is 10 times longer than that of the conventional 4-terminal MEMS relay.

In this paper, a 24 GHz phase-tunable resistively-coupled VCO is presented. The proposed VCO consists of two identical VCOs which are coupled through resistors. By differentiating free-running frequencies of two VCOs by controlling variable capacitances of their respective resonators, continuous phase difference between the VCOs upto 90° could be established. This shows the phase noise of −95.3 dBc/Hz and tuning range of 11.8 % with 18 mW DC power consumption. This is fabricated using 0.13 um CMOS process with its chip area of 1×1 mm2. The phase difference tuning capability of coupled oscillators can be used in some applications.

A fully on-chip SOI LDMOS linear PA for WLAN is implemented in a SOI LDMOS process. A cascode of SOI CMOS and SOI LDMOS is used to overcome the breakdown issue of the SOI CMOS transistor. An adaptive power cell (APC) and specially designed CG bias network are adopted to achieve linear performance. This proposed PA has gain of 24.3 dB and output power of 20.2 dBm for an 802.11n modulated signal with the EVM of −25dB.

The chip to chip data link receiver is implemented with the non-resonant plasma wave detector at 250 GHz. The receiver is composed with on-chip patch antenna, stacked FET detector, and limiting amplifier. The stacked FET detector detect THz signal by non-resonant plasma wave transistor. The non-resonant plasma wave transistor is based on the broadband direct detection well beyond the cutoff frequency of the technology. The on-chip patch antenna is designed by top metal and the bottom metal of the technology. The bandwidth of receiver is limited by baseband limiting amplifier. The limiting amplifier is designed by 5GHz bandwidth and 40dB voltage gain. The receiver is designed for 10Gbps on-off keying (OOK) communication. Demodulation at 4 kbps has been verified because of the limited modulation frequency of THz source. The chip to chip data link with non-resonant plasma wave transistor is firstly implemented by CMOS process.

This paper presents two kinds of linearization techniques for RF CMOS Power Amplifiers (PAs). One is the linearization technique using adaptively controlled biases of Common Source (CS) and Common Gate (CG) amplifier in a cascode structure The ethers are the power-cell linearization techniques such as large signal multi-gated transistor (LS-MGTR) of a CS amplifier and adaptive power cell (APC) of CG amplifier.

This paper presents a K-band FMCW radar transceiver IC, which is integrated in 0.13-μm CMOS technology. In the transmitter part, the class-C topology is adopted in the VCO block to achieve good phase noise performance. In the receiver part, the high gain of the LNA sufficiently suppresses the noise of the next stages to achieve a good noise figure in the receiver and the linearity of the receiver was improved by adoption of a gain control block, thereby achieving a wide dynamic range. As a result, a conversion gain of 35.7 dB, a P1dB of −12.7 dBm, and a DSB noise figure of 5.5 dB are achieved in the receiver part. The tuning range of 23.8∼24.5 GHz and the phase noise of −103.1 dBc/Hz @ 1MHz offset are achieved in the transmitter part. The transceiver chip consumes 181.5 mW from a 1.5 V power supply. Using this chip, the K-band FMCW radar module is implemented and verified by measurement of the distance of an object.

The 26 GHz and 79 GHz UWB frequency bands are used for short-range radar applications for automobile. In this paper, single chip front-end ICs for both frequency bands are presented. The pulsed oscillator at 26 GHz can produce UWB short pulses. It consumes power only during short duty cycles; thus, it allows a power-efficient radar. A stereo radar, which comprises two synchronized radars, is demonstrated with the ICs. Hybrid beam forming techniques based on base-band delay are also demonstrated. The pulsed front-end architecture of the proposed 79 GHz UWB pulse radar is discussed, which is expected to reduce power consumption. The performance of some circuit elements is also reported.

In this paper, a 79 GHz g m -boosted sub-harmonic mixer with high conversion gain is presented. As a g m -boosting technique, a transformer based feedback network with an NMOS bleeding path is proposed to achieve high conversion gain. The differential LO-driven sub-harmonic mixer has a simple structure and operates at low LO power. The measurement results show a conversion gain of 1.6 dB at a LO power of −5 dBm, a noise figure of 13 dB, and a 2LO-to-RF isolation of 38 dB. The power consumption of the sub-harmonic mixer is 12 mW. The circuit was fabricated using 65-nm CMOS technology with a chip area of 0.69×0.45 mm2.

This paper presents CMOS front-end ICs with 13.3 dBm output power for K-band FMCW radar, which is integrated in 0.13-μm CMOS technology. The transmitter consists of a voltage controlled oscillator, divider chain, power amplifier, and additional buffers. The receiver consists of a low-noise amplifier, IQ mixers, an IQ generator, and buffers. The leakage problem can be mitigated by adopting differential topology and ground shielding. As a result, the receiver achieves a conversion gain of 35.7 dB, a P1dB of -31.6 dBm, and a DSB noise figure of 5.5 dB. The transmitter achieves the tuning range of 23.8~24.5 GHz and the phase noise of -104 dBc/Hz @ 1MHz offset. The receiver and transmitter chips consume 121.5 mW and 373.5 mW from a 1.5 V power supply, respectively. Using these two chips, the K-band FMCW radar module is implemented and verified by measuring the distance of an object.

Highly integrated front end module (FEM) with selectively anodized aluminum substrate was proposed and designed from 2.3 GHz to 2.5 GHz for WiMAX/Wibro applications. It consists of a MMIC power amplifier (PA), a MMIC SPDT switch, and a LPF with integrated passive device (IPD) on the substrate. The PA and the SPDT switch were designed with 2 μm GaAs HBT process and 0.5 μm InGaAs pHEMT process, respectively. The performance of the PA is comparable with commercial WiMAX products. The FEM has the gain of 30.3 dB and EVM of 2.6 % at 23 dBm FEM linear output power with the help of aluminum substrate's good thermal dissipation, and its compact size is 4 × 5 mm2.

A fully integrated dual-mode CMOS power amplifier (PA) with nonlinear MOS capacitance compensation is presented using 0.18-μm RF CMOS process. The proposed technique is used to implement dual mode structure as well as reduces AM-PM distortion. Dual-mode output matching network using transmission line transformer (TLT) is implemented for efficient dual mode operation. With a supply voltage 3.5V, the PA has the power gain of 26.2 and 14.2dB in low power mode (LPM) and high power mode (HPM), respectively. The quiescent current is only 28mA at LPM. The maximum linear output power satisfying 3GPP WCDMA modulated signal is 28/16.3dBm with a PAE 33.8/10.2% in the HPM/LPM.

A 77GHz CMOS 4-channels receiver, transmitter with 3-outputs and array antenna architecture is proposed for low cost/small size automotive radar system, and implemented by using 65nm CMOS and LTCC substrate respectively. Measured performance of CMOS transceiver, which included useful functions such as dual operation of long/short range detection, I/Q signal process and gain attenuation when near target detection, shows comparable performances to that of commercial SiGe chips. Especially, the transmitter consumes one third lower power compared to SiGe chips. These results confirm that it may be a promising candidate for low cost and small size car radar system.

A 77 GHz CMOS medium power amplifier (PA) with high efficient matching networks based on transformer is presented. The unit transistor size of a power cell is selected by analyzing its maximum available gain. The broadside-coupled Transmission-Line Transformers (TLTs) are implemented as matching networks for low insertion loss and wide band matching characteristics. The PA is fabricated using a 65-nm RF CMOS process. The saturated output power and the peak power-added efficiency at 76.5GHz is 12.8 dBm and 8%, respectively. The DC power consumption is 236 mW with a supply voltage of 2.0V.

This paper presents a CMOS RF programmable-gain driver amplifier (RF PGDA) for wireless transmitters. Digital-step differential attenuators precede a programmable-gain amplifier in order to enhance the dynamic range and to save power consumption, especially at low gain region. The RF PGDA fabricated in 0.13-μm CMOS technology with a 1.2 V supply voltage achieves a dynamic range of 49 dB with a step error of less than 0.5 dB and highly-linearized output satisfying the WCDMA/LTE specifications.

A CMOS linear PA for IEEE 802.11 b/g applications is implemented in a 0.13 μm process including all matching networks. An adaptive power cell (APC) scheme is proposed to achieve high linear output power and efficiency and applied to the PA, which delivers the output power of 20.5 (19.5) dBm with the PAE of 20.2(17.5)% for an 802.11g modulated signal with the EVMs at -25(-28) dB.

Although a CMOS device has inferior characteristics for PA it allows versatile controls and possible integrations with other circuits. These advantages surely provide us various methods to linearize a PA with resultant high efficiency. Several linearization methods of RF CMOS PAs are introduced in this paper. These are mostly based on adaptively controlling the biases of common source and common gate power transistors with the input envelope in many different manners. The other type effort is shown for a power driver linearizer which is made of a digital vector modulator. As examples, RF CMOS PAs for WCDMA and WLAN are demonstrated.

Radio-frequency performance is limited by fundamental constraints in dynamic range, as CMOS scaling continues to push supply voltages lower. The receiver needs to reject large in-band and out-of-band blockers while detecting small desired signals. The transmitter needs to maintain high efficiency and low distortion, while processing signals with wider bandwidths and higher peak-to-average ratios to support high data rates. Recent developments in RF transceiver design utilize techniques that cancel noise and distortion in receiver and transmitter signal paths. Digital circuits and calibration are increasingly being used to aid radio performance and allow area reduction. This Forum will present advanced circuit design techniques that demonstrate the current state-of-the-art. System specifications will be discussed to provide context for the required circuit enhancements. The first three talks will focus on noise and distortion cancellation techniques used in receivers. The next three talks will focus on transmitter design including both digital and analog linearization techniques. Finally, the last talk will introduce in-device co-existence issues and solutions for wireless systems that require multiple radios operating concurrently. This Forum is aimed at circuit designers and engineers active in radio-transceiver and wireless-system design.

A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (P OUT ) at a 1-dB-gain-compression-power (P 1dB ) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.

This paper presents a low power UWB radar transceiver IC, which is used to make a radar system with precise range accuracy. The range accuracy is allowed by a variable delay circuit which can control the delay by 5 ps resolution. The detecting range of the transceiver is from 0.15 m to 8.4 m. The measurement results show that the maximum error is 3.75 mm. The circuit is implemented in a 0.13 µm CMOS process with the die area of 1.28 × 1.07 mm2. The total power consumption of the core circuit is 6.89 mA with the supply voltage of 1.5 V.

A CMOS centric phase array radar architecture is proposed for long range detection with a high angular resolution and short range with a large field of view at once. And one channel transceiver is implemented in a 65nm CMOS technology and patch array antenna also fabricated on LTCC (Low Temperature Co-fired Ceramic) substrate for small form factor, low power radar. Measured 77GHz I/Q receiver showed a 22dB conversion gain with dynamic gain range of 76dB. Two kinds of VCO showed 69.6∼81GHz and 75.2∼79.2GHz tuning range. A gain of 14.3 dB and P1 dB of 10dBm is obtained at transformer coupled two-stage cascade power amplifier. All the measured results showed a good agreement with simulated one up to 110 GHz by modeling of passive/active test devices and EM (Electro Magnetic) simulations, and showed a the promising candidate for automotive radar applications.

Integrating a CMOS RF power amplifier (PA) into a single-chip transceiver is one of the most challenging works in implementing radio front-ends, which presents many advantages in handheld applications [1,2]. Especially, low-power efficiency enhancement (LPEE) techniques, considering the probability distribution function of the practical wireless communication environments, extend the battery lifetime in handheld devices [1–3]. Therefore, there are many studies for the LPEE in handheld CMOS PAs [1,2] using transmission-line transformers (TLTs) with parallel amplifiers. Designing a series/parallel-combining transformer (SCT/PCT) is one of the key factors in the implementation of a dual-mode CMOS PA. However, the dual-mode performances of the PA must be optimized by using one output TLT structure. It is expected that there are difficulties in designing a highly efficient dual-mode PA. Therefore, this paper introduces a fully integrated dual-mode CMOS PA with a proposed output TLT with 2 control switches, which allows an LPEE with a back-off region of 10dB or more with a very low quiescent current.

A power amplifier, a phase shifter, a digital attenuator, and a transmit/receive (T/R) switch are fabricated for X-band phased array applications, which are implemented with CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascode structures. It provides 1-dB gain-compressed output power (P 1dB ) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8–11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of n-MOS transistors as a switch. It has 360° phase-control range with 5.6° phase resolution. It shows RMS phase and amplitude errors are below 5° and 0.8 dB, and insertion loss of −15.7 ± 1.1 dB. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employs compensation circuits for low insertion phase variation. It has maximum attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and 2° at 8–11 GHz frequencies, and insertion loss is −10.5 ± 0.8 dB. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of −1.5 dB, return loss below −15 dB, and isolation about −30 dB.

A digital-RF transmitter based on direct up-conversion with segmented cell structure is presented. The prototype is designed in 90-nm CMOS process. The implemented transmitter achieves an ACLR1 / ACLR2 of −37.89 dBc / −46.33 dBc for WCDMA and −37.19 dBc / −44.11 dBc for LTE with 5 MHz channel bandwidth.