Search

Your search keyword '"Sicard, Gilles"' showing total 92 results
Start Over Author "Sicard, Gilles" Publisher ieee
92 results on '"Sicard, Gilles"'

8. A 2-Stage EM Algorithm for Online Peak Detection, an Application to TCSPC Data.

Author

Poisson, Valentin, Guicquero, William, Coriat, David, and Sicard, Gilles

Abstract

Time-Correlated Single Photon Counting (TCSPC) sensors based on the combination of Single Photon Avalanche Diodes (SPADs), Time to Digital Converters (TDCs) and histogram-builders have become a standard for depth imaging using direct Time of Flight (D-ToF). However, one of the main current issue of this working mode is intrinsically due to the large amount of data required to generate pixelwise ToF histograms. To overcome this limitation, a 2-stage Expectation Maximization (EM) algorithm for online peak detection with its Register Transfer Level hardware implementation is proposed. The online estimator consists in sequentially computing the statistical parameters that directly encode the latent spatial distance and intensity information of the illuminated scene. The evaluation on synthetic data demonstrates that with a compression ratio of 0.4%, our approach can efficiently reduce the pixel pitch by around 40% without sacrificing timing resolution. [ABSTRACT FROM AUTHOR]

Published
2022
Full Text
View/download PDF

10. A 1Mb Mixed-Precision Quantized Encoder for Image Classification and Patch-Based Compression.

Author

Nguyen, Van Thien, Guicquero, William, and Sicard, Gilles

Subjects
WEIGHT training, IMAGE compression, INTEGRATING circuits, IMAGE processing, INTEGRATED circuits, CLASSIFICATION
Abstract

Even if Application-Specific Integrated Circuits (ASIC) have proven to be a relevant choice for integrating inference at the edge, they are often limited in terms of applicability. In this paper, we demonstrate that an ASIC neural network accelerator dedicated to image processing can be applied to multiple tasks of different levels: image classification and compression, while requiring a very limited hardware. The key component is a reconfigurable, mixed-precision (3b/2b/1b) encoder that takes advantage of proper weight and activation quantizations combined with convolutional layer structural pruning to lower hardware-related constraints (memory and computing). We introduce an automatic adaptation of linear symmetric quantizer scaling factors to perform quantized levels equalization, aiming at stabilizing quinary and ternary weights training. In addition, a proposed layer-shared Bit-Shift Normalization significantly simplifies the implementation of the hardware-expensive Batch Normalization. For a specific configuration in which the encoder design only requires 1Mb, the classification accuracy reaches 87.5% on CIFAR-10. Besides, we also show that this quantized encoder can be used to compress image patch-by-patch while the reconstruction can performed remotely, by a dedicated full-frame decoder. This solution typically enables an end-to-end compression almost without any block artifacts, outperforming patch-based state-of-the-art techniques employing a patch-constant bitrate. [ABSTRACT FROM AUTHOR]

Published
2022
Full Text
View/download PDF

15. Exploring Hierarchical Machine Learning for Hardware-Limited Multi-Class Inference on Compressed Measurements

Author

Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
Computational complexity theory, Computer science, business.industry, SVM, 020208 electrical & electronic engineering, Decision tree, Cognitive neuroscience of visual object recognition, compressive sensing, Inference, 02 engineering and technology, Hierarchical clustering, Hierarchical classifier, Support vector machine, ComputingMethodologies_PATTERNRECOGNITION, 0202 electrical engineering, electronic engineering, information engineering, embedded multi-class inference, 020201 artificial intelligence & image processing, Hierarchical learning, Cluster analysis, business, Classifier (UML), Computer hardware, clustering
Abstract

This paper explores hierarchical clustering methods to learn a hierarchical multi-class classifier on compressed measurements in the context of highly constrained hardware (e.g., always-on ultra low power vision systems). In contrast to the popular multi-class classification approaches based on multiple binary classifiers (i.e., one-vs.-all and one-vs.one [1]), a hierarchical classifier requires only O(log 2 C) binary classifiers in a decision tree. In this work, we investigate three clustering methods used to construct balanced clusters at each node thus reducing the depth of the decision tree in order to lower hardware requirements to its minimum. A binary Support Vector Machine (SVM) [2] classifier is then learned on Compressive Sensing measurements [3] at each node of the hierarchical tree. Our results, based on two object recognition databases (AT&T and COIL-100 databases), show the competitiveness of hierarchical classification in terms of hardware requirements (lower memory and computational complexity) as well as its classification accuracy.

Published
2019

16. An Analog-to-Information VGA Image Sensor Architecture for Support Vector Machine on Compressive Measurements

Author

Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
Video Graphics Array, Computer science, business.industry, Dimensionality reduction, SVM, 020208 electrical & electronic engineering, embedded object regognition, compressive sensing, Analog-to-digital converter, 02 engineering and technology, Facial recognition system, law.invention, Support vector machine, pseudo-random permutation, Compressed sensing, law, 0202 electrical engineering, electronic engineering, information engineering, Affine transformation, Image sensor, business, Computer hardware, Digital signal processing, Sigma-Delta
Abstract

This work presents a compact VGA (480 × 640) CMOS Image Sensor (CIS) architecture with dedicated end-of-column Compressive Sensing (CS) scheme allowing embedded object recognition. The architecture takes advantage of a low-footprint pseudo-random data mixing circuit and a first order incremental Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) to extract compressed features. The proposed CIS achieves an object recognition accuracy of ≃ 93% on the Georgia Tech face recognition database (GIT, 10 classes out of 50) thanks to a linear Support Vector Machine (SVM) classifier implemented by an optimized Digital Signal Processing (DSP). We stress that the signal independent dimensionality reduction performed by our dedicated CS scheme (1/480) allows to dramatically reduce memory requirements (≈ 32 kbit) related −in our case− to the ex-situ learned affine function of the linear SVM.

Published
2019

17. Exploring Hierarchical Machine Learning for Hardware-Limited Multi-Class Inference on Compressed Measurements

Author

UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique, Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique, Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, and 2019 IEEE International Symposium on Circuits and Systems (ISCAS)

Abstract

This paper explores hierarchical clustering methods to learn a hierarchical multi-class classifier on compressed measurements in the context of highly constrained hardware (e.g., always-on ultra low power vision systems). In contrast to the popular multi-class classification approaches based on multiple binary classifiers (i.e., one-vs.-all and one-vs.one [1]), a hierarchical classifier requires only O(log 2 C) binary classifiers in a decision tree. In this work, we investigate three clustering methods used to construct balanced clusters at each node thus reducing the depth of the decision tree in order to lower hardware requirements to its minimum. A binary Support Vector Machine (SVM) [2] classifier is then learned on Compressive Sensing measurements [3] at each node of the hierarchical tree. Our results, based on two object recognition databases (AT&T and COIL-100 databases), show the competitiveness of hierarchical classification in terms of hardware requirements (lower memory and computational complexity) as well as its classification accuracy.

Published
2019

18. Near Sensor Decision Making via Compressed Measurements for Highly Constrained Hardware

Author

UCL - SST/ICTM/INMA - Pôle en ingénierie mathématique, Benjilali, Wissam, Guicquero, William, Jacques, Laurent, Sicard, Gilles, UCL - SST/ICTM/INMA - Pôle en ingénierie mathématique, Benjilali, Wissam, Guicquero, William, Jacques, Laurent, and Sicard, Gilles

Abstract

This work presents and compare three realistic scenarios to perform near sensor decision making based on Dimensionality Reduction (DR) techniques of high dimensional signals in the context of highly constrained hardware. The studied DR techniques are learned according to two alternative strategies: one whose parameters are learned in a compressed signal representation, as being achieved by random projections in a compressive sensing device, the others being performed in the original signal domain. For both strategies, the inference is yet indifferently performed in the compressed domain with dedicated algorithm depending on the selected learning technique. Our results, based on two common datasets, show that performing the inference in the compressed domain represents a competitive approach compared to the classical classification strategy (inference in the original signal domain) regarding memory and computational requirements. We also exhibit the fact that it is especially well suited for embedded applications in the context of hardware implementations with limited resources even with specific hardware design and limitations.

Published
2019

26. Advanced 3D Technologies and Architectures for 3D Smart Image Sensors

Author

Vivet, Pascal, primary, Sicard, Gilles, additional, Millet, Laurent, additional, Chevobbe, Stephane, additional, Chehida, Karim Ben, additional, Angel Cubero, Luis, additional, Alegre, Monte, additional, Bouvier, Maxence, additional, Valentian, Alexandre, additional, Lepecq, Maria, additional, Dombek, Thomas, additional, Bichler, Olivier, additional, Thuries, Sebastien, additional, Lattard, Didier, additional, Severine, Cheramy, additional, Batude, Perrine, additional, and Clermidy, Fabien, additional

Published
2019
Full Text
View/download PDF

37. Hardware-Compliant Compressive Image Sensor Architecture Based on Random Modulations and Permutations for Embedded Inference.

Author

Benjilali, Wissam, Guicquero, William, Jacques, Laurent, and Sicard, Gilles

Subjects
IMAGE sensors, CMOS image sensors, DIGITAL signal processing, ANALOG-to-digital converters, IMAGE encryption, OBJECT recognition (Computer vision)
Abstract

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical (i.e., stable embedding, measurements incoherence) and practical requirements (i.e., silicon footprint, power consumption). The only additional hardware compared to a standard CIS architecture using first order incremental Sigma-Delta ($\Sigma \Delta $) Analog to Digital Converter (ADC) are a pseudo-random data mixing circuit, an in- $\Sigma \Delta ~\pm 1$ modulator and a small Digital Signal Processor (DSP). On the algorithmic side, three variants are presented to perform the inference on compressed measurements with a tunable complexity (i.e., one-vs.-all SVM, hierarchical SVM and small ANN with 1-D max-pooling). An object recognition accuracy of $\simeq 98.8$ % is reached on the COIL database (COIL, 100 classes) using our dedicated Neural Network classifier. We stress that the signal-independent dimensionality reduction performed by our dedicated CS scheme (1/480 in $480 \times 640$ VGA resolution case) allows to dramatically reduce memory requirements mainly related to the remotely learned coefficients used for the inference stage. [ABSTRACT FROM AUTHOR]

Published
2020
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results