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2. Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

3. Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors

4. Computer aided design of sub-100 nm strained-Si/Si/sub 1-x/Ge/sub x/ NMOSFET through integrated process and device simulations

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