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Classification of code script readability (which corresponds to categorizing a source code as either readable or unreadable) has prompted severe concern in academia and industry. To construct accurate classification models, previous studies depended mainly upon handcrafted features. However, the manual feature engineering process is usually labor-intensive and can capture only partial information about the source code, which is likely to limit the model performance. To improve this, we propose the use of GAN's (Generative Adversarial Networks). First, we present a representation approach (with multiple granularities) to encode source codes as the input to GAN's into integer matrices. Then we propose an EGAN based on GAN's for the code readability classification. EGAN consists of three separate GANs with identical architectures that are trained on data preprocessed in different ways. We evaluate our approach against five state-of-the-art code readability models. The findings of the tests demonstrate that RGA can surpass previous approaches. The quality increase varies from 2% to 15%. EGAN offers reasonably improved performance by removing the need for manual interface design, demonstrating the usefulness of GAN's approaches in code readability classification tasks.

This work addresses the field of human-robot collaboration, in particular, the hand-guidance of a redundant mobile manipulator. An efficient hand-guidance is related to the improvement of the inertial properties of the end-effector felt by the operator, as these describe the effort to guide the robot. In this regard, the operational space formulation is used to minimize the effective mass in the null space of the hand-guidance task. The minimization is based on a geometric ellipsoid representation and applies a gradient descent method. The approach is tested on the KUKA VALERI mobile manipulator and implemented on a real-time framework, whereby a particular focus is on stability and safety. For this purpose, a power limitation is proposed. Finally, the improvement of the effective mass related to a specific direction is discussed.

In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.

Multi-class analysis, as the term suggest is the classification of the data in more than two classes. However not much studies were focused on such analysis and researchers often confined themselves to the binary sentiment classifiers. In this paper, we proposed machine learning algorithm as an approach to predict the sentiment classification. The experiments are conducted on public data sets combined with ensemble method named BAGGING, an abbreviation for Bootstrap aggregation with 10-cross fold validation technique is used to obtain the classification accuracy. The result accuracy suggested the exploring further improvement using the combination of the multi-class sentiment classifiers.

Extending tungsten contact for the most advanced nodes (≤ 7 nm) is challenging due to the growing impact of contact resistance on the overall resistance of a device and to the increasing difficulty of gapfill in features with < 20 nm critical dimensions. The paper presents a gapfill material using metalorganic chemical vapor deposition (MO-CVD) cobalt for contact plug. Highlights of new gapfill material include proven seamless, voidless gapfill and contact resistance reduction. CVD Cobalt anneal parameters are discussed that can be optimized in combination with the deposition process to achieve desired gapfill. A proprietary electron-beam imaging technology was used to qualify the cobalt fill for void-free performance. Various process flows are discussed that lead to the best-known fill and resistance reduction values.

In organization numbers are increasing day by day with a drastic pace which prefers the extraction of the workflow of processes to interpret the operational processes. For a viably and sorted out approach to drive the development in the realm of digitization is utilized by the approach of work process extraction. The work process extraction/mining are otherwise called process mining. The goal of Workflow mining is to get the extraction of data of an association's method of business by changing over the logs of occasion information recorded in association's frameworks. This impact to the enhance conformation of processes to organization regulation where workflow mining approach for analysis is actualized. Work process Mining strategies are absolutely rely upon the nearness of framework occasion log information. We accept to involve setting various endeavors on building our strategies or frameworks to record the greater part of the old information. The urge to comprehend and expand their procedures of businesses entails the process exploration practices. This paper displays a philosophy how programming occasion log information is analyzed to grasp and advance the product work process by utilizing arrangement which best in class utilized as a part of the product code clone streamlining for the human services area application.

We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (pc) down to 2.1×10−9 Ω.cm2 (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P with a ρ c at 2.6×10−9 Ω.cm2 is measured. We demonstrate up to 90% superconformality for this process, with a tunnel silicidation at lengths up to 500nm, showing an exceptional selectivity to oxide. This process is an enabler for the next generation of area-enhanced contact CMOS architectures.

A Programmable Logic Controller (PLC) based power factor correction method for a 3-phase Induction Motor (IM) through switching of shunt capacitors is proposed in this paper. A 3 phase IM has a low power factor (pf) at no load as it draws large magnetizing current and the active power delivered to the motor is low, which is utilized to overcome the no-load losses. The PLC based power factor improvement algorithm is developed and implemented on a 3 Phase laboratory prototype IM coupled to a DC generator and the effectiveness of the algorithm is tested under no-load and loaded condition. Based on the instantaneously measured value of power factor, the PLC switches the appropriate bank of capacitors into the circuit depending on the load condition to improve the pf. Large scale use of PLC in industrial automation, adaptability, simple implementation and economics justified its selection as the switching controller. A significant improvement in power factor under different loading conditions is observed.

We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the source/drain, self-aligned on the contact trench. A record low p-type contact resistivity of 5.9×10−9 ohm-cm2 is demonstrated and a 7.5% performance improvement is achieved. The variation of the implant temperature demonstrates a further improvement of the contact resistance when going to cryogenic (cold) implantation (−100 °C). Using TCAD, we demonstrate that the reduced implant temperature provides a higher degree of amorphization and reduces defects. This is the key to provide an enhanced recrystallization of the doped amorphized region through Solid Phase Epitaxial Regrowth (SPER) low temperature activation. We propose in this paper a novel mechanism for p-type contacts, and demonstrate it for the first time on state-of-the-art FinFET p-type devices using cryogenic (cold) implants and SPER regrowth.

We report a record-setting low NMOS contact resistivity of 1.2×10−9 Ωcm2 compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ C to below 1×10−9 Ωcm2 for the post 7 nm nodes.

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e−8 to 2.8e−9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

In recent times, the ease in availability and usability of digital video editing tools has become a major challenge to video forensic experts, to accurately authenticate any suspected digital video content. Besides, the wide range and rapid advancement in the field of such editing tools and improvements in anti-forensic techniques has enabled any naive user to edit, alter, and modify any digital video with minimal traces/footprints. Recent surveys in the field of digital video forensics highlight the need of research in this field. The requirement of authenticating the integrity of the contents of digital videos ranges from an individual to organizations, defense and security setups to law enforcement agencies. Further to it, the need to explore newer and more effective Passive (or Blind) video forgery detection approaches is gaining importance day by day. This is attributable to the fact that digital videos are accepted as evidences in most of the countries and real life cases involving tampered digital videos, more often than not, rarely get supplemented by any other reference information besides the suspected video. This paper aims at highlighting the challenges and brings out opportunities in the field of Passive or Blind digital video forensics, focusing on spatio-temporal or copy-move attacks on digital videos, by reviewing the existing literature and research work in this field.

Due to the advent of social media and networking sites, people now have the opportunity to communicate with each other more easily and frequently than ever before. The analysis of the content of these communications can lead to numerous benefits to the governments and corporations across various industries. These will allow them in gauging the public sentiment on a multitude of items and issues, on which they can take necessary actions. However, to do so, one needs to decipher the content which is usually in the form of a complicated mix of multiple languages. In Indian social media, users often combine Romanized English with their mother tongue language for communications. In this paper, we have presented a number of techniques to identify the sentiment of text after normalizing the influence of multiple languages.

The field of getting insights from various text forms such as feedback, opinions, blogs and classifying them based on their polarity as positive or negative is known as sentiment analysis. But from last few years we find huge amount of code - mix (mixture of two languages) text available on social media. This text is available in Romanized English format in Indian social media, which is the transliteration of one language into another, which demands normalization to get further insights into the text. In this paper, we have presented various methods to normalize the text and judged the polarity of the statement as positive or negative using various sentiment resources.

We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

The 10−7 nm CMOS nodes require that ρc be reduced to < 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

This paper mainly focuses on the analysis of the various factors which are responsible for affecting the performance of a solar PV system. However, the performance is judged on the basis of the power output from the panel, so the analysis will be done for the factors which directly or indirectly affect the power output of Solar PV systems. The real time data is collected from the solar panel installed at the roof tops of the Electrical Engineering Lab Building of D.E.I., University, Agra, U.P. India. This paper provides an analysis of a study of the photovoltaic system's performance in real time and the factors affecting it such as partial shading, dust and temperature. Shading on PV panel may be due to shade of the long trees standing nearby the system, shade from the other parallel row of the panel, the shade due to birds sitting on the panel etc. Dust is also an important factor that degrades the panel rating. The temperature effect on the current and thus the power rating of the panel is also considered in this paper.

Automated detection of neonatal sleep apnea is essential for constrained environments with high patient to nurse ratio. Existing studies on apnea detection mostly target adults, and use invasive sensors. Few approaches detect apnea using video monitoring, by identifying absence of respiratory motion. They apply frame differencing and thresholding, not suitable for neonates due to their subtle respiratory motion intermixed with other body movements. Proposed method first applies motion magnification. Subsequently, it filters respiration motion using dynamic thresholding. The technique is benchmarked with simulated motion of varying respiration frequencies. When validated with neonatal video data, proposed method achieves both > 90% sensitivity and specificity.

Low specific contact resistivity (7E-9 Ohm.cm2) was achieved for contacts with TiSi x to in-situ epitaxially doped Si:P n-SD regions by use of Se implantation prior to Ti deposition. The key to this achievement is the optimization of implant energy and dose, and use of millisecond laser anneal to heal the implant damage, while allowing sufficient inter-mixing of Ti, Si, Se and P atoms across a smooth TiSi x /Si:P interface, to realize the SBH-lowering benefits of Se.

Contact resistivity (ρ C ) reduction for n-SD (source/drain) with Se+ implant was evaluated for different integration schemes. It is found that Se+ implant energy is one of the most critical process parameters for ρ C improvement, achieved by placing the Se+ peak close to silicide (TiSi 2 or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved with millisecond laser anneal, while minimizing dopant deactivation. This work demonstrated a viable integration pathway to realize low ρ C solution for n-SD for 10 nm node.

In present times software reengineering has become an important domain of research to increase the shelf life of legacy system. The major objective for reengineering revolves around reducing the cost of investment in Information Technology (IT) infrastructure by reducing the maintenance cost and capitalizing on the current existing IT infrastructure. This can be achieved by making it more adaptable to the changing requirements. The decision for reengineering system is quite challenging as one has to select from the available option of investing in new system or legacy system. Further cost of reengineering is not a true decisive parameter for taking up reengineering. A better approach is finding out return on investment (ROI). ROI of reengineering a system is difficult to calculate as one has to assume the cost of project and the project also depends on the requirement of reengineering. This paper gives a generalized approach towards decision making for reengineering the legacy system. This paper presents a requirement specific approach of cost estimation and proposes ROI computation for the assessment of reengineering.

In present times software reengineering has become an important domain of research to increase the shelf life of legacy system. The major objective for reengineering revolves around reducing the cost of investment in Information Technology (IT) infrastructure by reducing the maintenance cost and capitalizing on the current existing IT infrastructure. This can be achieved by making it more adaptable to the changing requirements. The decision for reengineering system is quite challenging as one has to select from the available option of investing in new system or legacy system. Further cost of reengineering is not a true decisive parameter for taking up reengineering. A better approach is finding out return on investment (ROI). ROI of reengineering a system is difficult to calculate as one has to assume the cost of project and the project also depends on the requirement of reengineering. This paper gives a generalized approach towards decision making for reengineering the legacy system. This paper presents a requirement specific approach of cost estimation and proposes ROI computation for the assessment of reengineering.

Graph algorithms play a prominent role in several fields of sciences and engineering. Notable among them are graph traversal, finding the connected components of a graph, and computing shortest paths. There are several efficient implementations of the above problems on a variety of modern multiprocessor architectures. It can be noticed in recent times that the size of the graphs that correspond to real world data sets has been increasing. Parallelism offers only a limited succor to this situation as current parallel architectures have severe short-comings when deployed for most graph algorithms. At the same time, these graphs are also getting very sparse in nature. This calls for particular work efficient solutions aimed at processing large, sparse graphs on modern parallel architectures. In this paper, we introduce graph pruning as a technique that aims to reduce the size of the graph. Certain elements of the graph can be pruned depending on the nature of the computation. Once a solution is obtained for the pruned graph, the solution is extended to the entire graph. We apply the above technique on three fundamental graph algorithms: breadth first search (BFS), Connected Components (CC), and All Pairs Shortest Paths (APSP). To validate our technique, we implement our algorithms on a heterogeneous platform consisting of a multicore CPU and a GPU. On this platform, we achieve an average of 35% improvement compared to state-ofthe-art solutions. Such an improvement has the potential to speed up other applications that rely on these algorithms.

The effects of anneal sequences (ms anneal followed by spike anneal vs. spike anneal followed by ms anneal) were explored. Substantial anneal sequence effects on dopant activation were also reported.

The continuing reduction of contact resistivity (ρC) is a critical challenge for device performance. In this paper the ρC reduction for n-SD (source/drain) is demonstrated using post-silicide implantation of Se or P into Ni(Pt) silicide, with various energies/doses and laser anneal conditions. The improvement of ρC is achieved without sacrificing junction integrity/leakage. Hence laser assisted post-silicide implantation can be a key enabler to realize low silicide contact for n-SD for the 14 nm node and beyond.

We present a web-based environment along with an interactive interface for VLSI schematic design, simulation, and layout design. It consist of 10 experiments starting from transistor level design of inverter, then some basic gates such as NAND, NOR, XOR etc, finally design of D latch and flip flop. In each experiment student will learn how to design VLSI circuits both schematic and layout. It also consists of experiment components such as objective, introduction, quiz, and theory etc. which gives step by step explanation of each experiment. It is a powerful self learning supplement for the VLSI design course offered in undergraduate engineering program. Along with teaching schematics and layouts of circuits, this virtual lab also consists of some experiment explaining about SPICE coding, VHDL and Verilog coding. An interactive panel is given in which student will write programming codes, simulate and see real time waveforms. The web based schematic and layout editor is designed to maintain the commonality with EDA tools such as Cadence Virtuoso, HSpice Cosmos, Tanner tools etc.

Si nanowires grown from TiSi2 catalysts exhibit near-infrared photoluminescence (PL) from quantum-confined excitons in the Si. Temperature dependent studies highlight the differences between Si nanocrystals and nanowires, which allow for exciton diffusion

Self-assembled Si nanowires can be grown using chemical vapor deposition accelerated by metal catalyst nanoparticles. The diameter of the nanowires depends on the size of the nanoparticles, which in turn can be controlled by varying the amount of catalyst deposited and the annealing conditions. The nanowires make good electrical connection to the substrate on which they are grown. They generally grow epitaxially along directions and can grow laterally from one vertical (111)-oriented surface toward another and make good mechanical and electrical connection to the second surface. The nanowires can serve as sensors or as the channels of field-effect transistors.