Search

The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the emitter side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.

The mechanism of reverse recovery failure in the lateral integrated Bootstrap Diode (BST-Diode) is investigated through physical TCAD simulation in this paper. It is found that the crowding of electric potential lines in the vicinity of the outermost anode metallization and the cathode region cause two high electric field peaks and severe impact ionization at the anode and cathode sides. Consequently double-sided dynamic avalanche occurs and reverse recovery failure takes place. An optimized structure with several disconnected P+ dynamic field limiting rings (DFLR) at the anode side is proposed. The reverse recovery robustness of the optimized diode is improved by more than 200%.

The impact of depletion in substrate on turn-off characteristic of superjunction (SJ) silicon-on-insulator lateral gate bipolar transistor is investigated in this paper. It is found that the depletion in substrate could lead to an increase of turn-off loss. The depletion layer expands deeply in P-type substrate (P-sub) with low doping concentration, which modulates the electric potential distribution and slows down the carrier extraction in SJ pillars. The reduced turn-off loss can be obtained by adopting a high-doped P-sub.

In this paper, a high-voltage silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) for high turn-off speed and low turn-off loss (E OFF ) is proposed. The device features an Assistant-Depletion Trench (ADT) shorted with the P+ emitter and a partial P-type Buried Layer (PBL) at the bottom of the drift region. The ADT together with the PBL accelerates the depletion of the drift region, which benefits to fast extraction of stored carrier during turn-off period. The simulations demonstrate that the proposed SOI-LIGBT exhibits a superior tradeoff between turn-off loss (E OFF ) and on-state voltage drop (V ON ) to the conventional SOI-LIGBT. E OFF of the proposed SOI-LIGBT is 69% lower than that of the conventional SOI-LIGBT at the same V ON of 1.53 V.

In this paper, the effect of irradiation-induced defects on the reverse recovery (RR) characteristics of the double-epitaxy SJ-MOSFET is investigated and modelled for the first time. Combinating theoretical modeling with numerical simulation, it is found that the first epitaxial layer thickness (W1) and the characteristic parameters of trap energy level both have a great influence on the RR. In addition, simulation results indicate other electrical characteristics of the device such as breakdown voltage and leakage current are also affected by them. Finally, we provide irradiation technology engineers with an effectual proposal to achieve a good compromise between RR and other electrical characteristics by choosing the appropriate W1, the trap energy level, and the size of carrier capture section.

An ultra-low reverse recovery charge (Q rr ) Cell-Distributed Schottky Contacts (CDSC) Superjunction MOSFET (SJ-MOSFET) is proposed in this paper. The proposed structure features that an isolated lateral NMOS is integrated in p-body region of SJ device. The conduction of the SJ-VDMOS intrinsic diode can be effectively suppressed by the reversed body diode of the integrated NMOS, which almost eliminates hole current in the voltage-sustaining layer during freewheeling period. Combining the CDSC with the integrated NMOS, an excellent reverse recovery characteristic of body diode in SJ-MOSFET is realized. The simulated results show that the proposed SJ-MOSFET can achieve a 97% and 91.8% lower Q rr compared with the conventional and the CDSC SJ-MOSFETs at the same IF of 3.2A. Moreover, the Figure-of-Merit ( $\mathbf{FOM} =\mathbf{R}_{\mathbf{on},\mathbf{sp}}\cdot \mathbf{Q}_{\mathbf{rr}}$ ) of the proposed structure is only $29.3\mathbf{m}\mathbf{\Omega}\cdot \mathbf{nC}$ , which is much superior to that of the conventional and the CDSC SJ-MOSFETs.

In this paper, we have proposed an enlightening and feasible process concept for irradiated Super-Junction Vertical Diffusion Metal Oxide Semiconductor (SJ-VDMOS) to realize fast reverse recovery of its body diode and maintain the stable threshold voltage for the first time. Twice epitaxy is adopted in this process concept. The electron irradiation is performed after the first epitaxy, and then the second epitaxy is conducted. Silicon etching and p-pillar refilling will be done afterwards. The fast reverse recovery of body diode is obtained by introducing the deep energy levels in the drift region, and the stable threshold voltage (V TH ) can be achieved due to the p-body region and the gate oxide are not suffered from electron irradiation. Combining experimental results with simulated verification, this process concept presents a huge potential of realizing high reliability and high stability among irradiated devices.

This paper investigates the influence of emitter-side deep-oxide trenches (EDOT) on dynamic avalanche capability of SOI lateral IGBTs. The EDOT can modulate the electric filed (E-field) and carrier distributions under dynamic avalanche conditions. The enhanced electrons injection and strengthened emitter-side E-field result in wide positive differential resistance (PDR) branches. The reduced hole current density in the silicon region beneath the N+ emitter contributes to high latch-up immunities. The hot spot at the edge of P-body can be weakened due to the suppressed impact ionization and alleviated carrier crowding. The wide PDR branch, high latch-up immunity and weak hot spot indicate an enhancement of dynamic avalanche capability, which is of great significance for monolithic power ICs operating under high voltage, high current, high dv/dt and/or high di/dt conditions.

A high-speed and high-ruggedness 600V PiN diode with the recessed anode and the double-side Schottky is presented. In on-state, the recessed anode shortens the electron current path from the i-layer to the anode electrode and the P- Schottky contact lowers the electron barrier, which reduces the hole injection efficiency at the anode side effectively. The fast recovery is realized due to the reduced amount of the stored carrier and the shortened carrier extraction path. The proposed structure achieves a reverse recovery time (t rr ) of 81ns which is improved by 43% comparing with the conventional structure at the same forward voltage drop (V F ) of 0.99V. Moreover, the high dynamic ruggedness of reverse recovery can be achieved by extra hole injection from the N-buffer surface through the N Schottky contact.

The type II short-circuit failure mechanism of trench gate insulated gate bipolar transistor (IGBT) is investigated in detail. By using physical TCAD simulations and experiments, it shows that high hole current goes along the trench gate which restructures the electric field distribution under the bottom of the trench gate. As a consequence, a dynamic peak voltage appears under the bottom of trench gate, which results in the gate oxide breakdown during the type II short-circuit process. An optimization structure with reducing the trench gate depth is proposed to suppress the dynamic peak voltage and improve the type II short-circuit robustness for trench gate IGBT.

A high-voltage SOI-LIGBT with high turn-off speed and low turn-off loss (E OFF ) is proposed in this paper. The proposed SOI-LIGBT features a Low-doped Buried N-layer (LBN) region and an emitter-side Electric Potential Modulation Trench (EPMT) shorted with the P+ emitter. By employing the LBN and EPMT, fast extraction of the stored carrier and the high turn-off speed are realized due to the accelerated depletion of N-drift region. The simulated results show that the proposed SOI-LIGBT can achieve a 73% lower turn-off loss compared with the conventional SOI-LIGBT at the same V ON of 1.52V. Moreover, the hole heat flux distribution in the proposed device predicts an improvement of ruggedness under high-voltage and high-current conditions.

The vibration character of a vehicle frame is important to the vehicle's performance and life. A geometry model of a jeep-like vehicle is created by Pro/E 4.0. Modal analysis of the vehicle frame is made and its vibration frequency and characteristics are achieved. The results are shown that the design of the vehicle frame is correct. Comparison of the Block Lanczos solution and the subspace solution of finite element method show that the precise of the subspace solution is higher and vibration characteristics are more regular. In contrast with the subspace solution, the computing time of the Block Lanczos solution is litter. If the computing precise is not very high in fact, the choice of the Block Lanczos solution should be selected.

Probabilistic Multi-Hypothesis Tracking (PMHT) is an algorithm for multiple target tracking when association of measurement and track is unknown. PMHT is an efficient algorithm for GMTI in cluttered environments of which the computational complexity is linear in the number of targets and measurements. An algorithm is presented in this paper to apply road information to PMHT. Road information is used to adjust estimated target state during the process of Kalman filter. Tracking performance of PMHT is increased apparently with the application of road constraint.

Automatic target recognition (ATR) of aircrafts using translation invariant features derived from high range resolution (HRR) profiles and multilayered neural network is presented in this paper. The HRR profile sequences are translation variant in the range resolution cell because of the non-cooperative target maneuvering. The differential power spectrum (DPS) is introduced to extract the translation invariant features. Several learning algorithms of feed-forward neural network are implemented to determine an optimal choice in the recognition phase. The range profiles are obtained using the two-dimensional backscatters distribution data of four different scaled aircraft models. Simulations are presented to evaluate the classification performance with the DPS based features and neural networks. The results show that this method is effective for the application of radar target recognition.

Generalized information cut (GIC) based on the nonlinear feature mapping using the kernel function is invariant for the linear transformation and the coordinates shift. By comparison and analysis of the angle similarity measurement and generalized information cut, the criterion of generalized information cut is proposed to solve the automatic target recognition using high resolution radar range profile. Feature mapping and inner product is synthesized in the feature space. The range profile data established from four different scaled aircraft models in unclassifiable low dimensional space is mapped into classifiable high dimensional space via the kernel function, and then the linear classifiable pattern transformed from nonlinear unclassifiable pattern is accomplished. Experimental results suggest that the target recognition technique based on the proposed method achieves better anti-noise performance, and is much more efficient in the improvement of recognition ratio of four different aircrafts than using the conventional angle similarity coefficient (the vectorial angle cosine).

The beam agility and controllability of system parameters provide phased array radar systems the capability of concurrent multifunction and the potential of high adaptability. It is very important to allocate the constrained radar resources to the radar tasks adoptively according to the dynamic change of the environment and the operational requirements in order to optimize the overall performance of the systems. The optimal model of the allocation of the radar resource is presented based on the quantified radar load in this paper. The parameter optimization of the search function of a Pulse-Doppler phased array radar is investigated, the method to design optimal search in an adaptive way is formulated and the impact of the model parameters on search performance is analyzed through simulations.

In recent years, passive localization and tracking are widely studied. Passive Time Difference Of Arrival (TDOA) system is one of important passive location systems. The IMM algorithm is a promising algorithm for tracking maneuvering targets. Here, a new application of IMM tracking algorithm to passive TDOA system is studied. The good tracking performance can be achieved if the accurate target motion models are selected. The paper presents a hybrid model of target motion, called CV-Singer model. Compared with the single model filter and the IMM filter used CV-CA model, the IMM filter used CV-Singer model can provide better tracking performance for passive TDOA systems.