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Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dithering. This work presents a mathematical model for dithering DTC-based local oscillator (LO) generators. It proposes concepts for the application of subtractive dither and it introduces a novel generalization of quantization-dither to allow for optimal dithering of nonlinear quantizers. [ABSTRACT FROM AUTHOR]

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm2. [ABSTRACT FROM AUTHOR]

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts. Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all the FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples, illustrating the developed theory. [ABSTRACT FROM PUBLISHER]

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples illustrating the developed theory. [ABSTRACT FROM PUBLISHER]

Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PH)), the loop filter, the voltage control osicllator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PH) reset delay mismatch. A simple analytic expression shows the level of δ &seegma; E sequence noise caused by static CP current mismatch. We further show that unequal rise time and fall lime constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PH) is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations. [ABSTRACT FROM AUTHOR]