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In this work, a 12-channel 120-Gb/s optical receiver array is realized in a 0.18-mum CMOS process. Optical receiver array consists of transimpedance amplifier (TIA) and limiting amplifier (LA). To enhance the bandwidth without deterioration of the other performance, advanced common-gate input configuration, active feedback technique, and negative impedance compensation are exploited. Post-layout simulations demonstrate that a single channel optical receiver achieves 96-dBOmega transimpedance gain (ZT), 10-Gb/s operations with 7.1- GHz bandwidth for 0.5-pF photodiode capacitance, and -20-dBm optical sensitivity.

Tactile sensation is one of the most important sensory functions along with the auditory sensation for the visually impaired because it replaces the visual sensation of the persons with sight. In this paper, we present a tactile display device as a dynamic Braille display that is the unique tool for exchanging information among them. The proposed tactile cell of the Braille display is based on the dielectric elastomer and it has advantageous features over the existing ones with respect to intrinsic softness, ease of fabrication, cost effectiveness and miniaturization. We introduce a new idea for actuation and describe the actuating mechanism of the Braille pin in details capable of realizing the enhanced spatial density of the tactile cells. Finally, results of psychophysical experiments are given and its effectiveness is confirmed.

In this study, the structural, dielectric and piezoelectric properties of Pb[(Ni/sub 1/3/Nb/sub 2/3/)/sub x/ - (Mn/sub 1/3/Nb/sub 2/3/)/sub 0.09-x/ (Zr/sub 0.505/Ti/sub 0.495/)/sub 0.91/]O/sub 3/ (x = 0, 0.01, 0.02, 0.03, 0.04, 0.05) system ceramics were investigated to develop the composition for piezoelectric transformers. All the specimens were sintered at 1250/spl deg/C and their physical properties were measured, and the results are as follows; With increasing PNN substitution for PMN-PZT system, the dielectric constant was increased and the electro-mechanical coupling factor (kp) was increased to 0.62 at 5 mol% while the mechanical quality factor (Qm) decreased.

High performance 90 nm CMOS transistors have been developed using channel epitaxy, poly Si/sub 1-x/Ge/sub x/ gate, elevated source/drain (S/D), and nickel salicide (NiSi) technologies with boron-penetration-free 20 /spl Aring/ gate dielectric. For the first time, these novel technologies are employed all together, and, merits and demerits are characterized in the high performance limit. For NMOS, I/sub dsat/(saturation-current)=890 /spl mu/A//spl mu/m at V/sub dd/=1.5 V, I/sub doff/(off-current)=1 nA//spl mu/m with improved linear and saturation transconductances has been achieved using channel epitaxy. For NMOS, I/sub dsat/=355 /spl mu/A//spl mu/m has been achieved using NiSi with significantly reduced junction leakage and gate R/sub s/. The junction capacitance has been reduced by 40% using elevated S/D, while the level of gate poly depletion has been reduced using poly Si/sub 1-x/Ge/sub x/ gate. Especially, a PMOS transistor using all novel technologies has been fabricated with L/sub gate/(gate-length)=145 nm for better manufacturability. This device has exhibited all superior characteristics described above at the same time, as a result, the PMOS gate delay is estimated to be reduced by 21%. It is important to note that this device is apt for the volume production of high-speed logic LSIs.

Silicon-on-Insulator devices having a buried capacitor structure have been proposed by several authors as a 1 giga bit DRAM cell structure. However, several limits such as wafer cost, low throughput, and poor SOI thickness uniformity would prevent the practical application of this technology in spite of its distinct advantages such as shorter process step, easier backend process, and higher packing density. In this paper, we demonstrated the feasibility of a novel pattern transfer method combining the hydrogen implantation and selective polish stop process which can be applied to the fabrication of buried capacitor SOI structure with a low cost and high throughput.

A novel method for low temperature deposition of conformal TiN is reported. ACVD (advanced chemical vapor deposition) is a TiCl/sub 4/-based TiN deposition process which relies on the surface reactions of the adsorbed precursors. With this technique, conformal TiN films with resistivity as low as 130 /spl mu//spl Omega/-cm can be deposited at a deposition temperature of 500/spl deg/C and below. The results from the integration of ACVD-TiN with Si contacts and vias in high density devices indicate that ACVD-TiN is applicable to all levels of multilevel metallization for the next generation of ULSI devices.

The (Sr/sub 1-x/Ca/sub x/)TiO/sub 3/(SCT) thin films are deposited on Pt-coated electrodes (Pt/TiN/SiO/sub 2//Si) using RF magnetron sputtering. The structural and dielectric properties of the SCT thin films were influenced by substitutional contents of Ca. The composition of SCT thin films was close to stoichiometry (1.081/spl sim/1.117 in A/B ratio). The maximum dielectric constant was obtained for a SCT15 thin film. The dielectric constant changes almost linearly in the temperature range -80/spl sim/+90[/spl deg/C]. The temperature properties of the dielectric loss have a stable value. The drastic decrease of dielectric constant and increase of dielectric loss in SCT thin films is observed above 100[kHz].

Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below 2.0 nm were fabricated and characterized. Super-steep retrograde channel profiles using boron (NMOS) or arsenic (PMOS) channel implantation followed by selective epitaxial growth of undoped-Si were found to effectively reduce short-channel effect and improve current drivability even in the sub-100 nm regime. For NMOS, indium implanted devices showed better short-channel immunity, however, no improvement in current drivability was observed. Optimization of the gate oxide thickness versus gate length was investigated in the presence of direct tunneling leakages and for the first time, an experimental guideline of oxide scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm stack gate dielectrics of oxynitride and LPCVD nitride were developed, which showed excellent transistor characteristics.