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The Muon g-2 Experiment at Fermilab will measure the muon magnetic moment with unprecedented precision (0.14 ppm), that is a fact or 4 improvement with respect to the previous measurements at BNL (E821). To achieve this uncertainty the relative response of each calorimeter channel must be calibrated and monitored at a level better than 10-3 in the time window of the muon fill. The calibration system is based on laser source and photo-detectors. The data acquisition of the system is designed around two FPGA based boards and a custom crate bus. The front-end board, which is slave, manages the photo-detector operation and signal processing, also performs a first level data concentration task. Up to 12 slave boards can be housed in a 6U crate and controlled by a readout master board which implements the event building functionalities and manages the interface for monitoring, electronic calibration and debugging tasks. A gigabitethernet interface of the board is used to transfer data to the online farm for storage and further processing. At present the system is working at FNAL. In this work we describe the design of the DAQ system, the Run Control for user interface and monitoring tasks with an evaluation of the system performance.

Time measurements play a crucial role in trigger and data acquisition systems of high-energy physics experiments, where synchronization between system elements, signal calibration, and phase-measurement accuracy is often required. In this paper, we present a fully digital time-to-digital converter (TDC) architecture and its application, based on a synthesizable digitally controlled oscillator (DCO), where the TDC is used to measure the phase relationship between a timing signal and a 40-MHz reference clock. The DCO design is technology independent; it is described by means of a hardware description language and it can be placed and routed with automatic tools. The TDC will be used in the new readout chip that is under development for the muon detector electronic upgrade in Large Hadron Collider beauty experiment at CERN. The TDC presented in this paper has the fundamental task of measuring, with a resolution of about 1.5 ns, the phase difference between the 40-MHz LHC machine clock and a digital signal coming from the muon detector.

Trigger and data acquisition systems (TDAQ) of High Energy Physics (HEP) experiments intensively use time measurements for calibration of signals and synchronization between their different elements. Typically, electronics systems for time measurement are designed using a classical mixed-signal approach, while all-digital architectures are nowadays being explored and studied by state-of-art research. Indeed, although an optimized mixed-signal design reaches better performances, it requires a significant amount of design time w.r.t. a fully-digital design. Moreover, an analog IP blocks cannot be easily ported into a new technology, if compared with full digital IPs. In this work, we present a fully-digital TDC application, which is based on a fully synthesizable DCO. The TDC measures the phase relationship between a 40 MHz reference clock and a timing signal under measurement. The DCO design is independent from the technology and it can be described by using a high level Hardware Description Language; moreover, due to its specific characteristics, it can be synthesized, placed and routed by using automatic tools. In this work, we present the architecture of the DCO and of the TDC, their performances and the results on a preliminary implementation on a 130 nm ASIC prototype. The TDC is planned to be used in the upgrade of the Muon detector readout electronic in LHCb experiment at CERN. The TDC presented in this paper has the task of measuring the phase difference between the 40 MHz LHC machine clock and a digital signal coming from the muon detector. One of the main constraints of the TDC is on the phase difference resolution, which has to be about 1.5 ns, in order to cope with to the required resolution of the experiment.

The ARGO-YBJ experiment has been in stable data taking since November 2007 till February 2013 at the YangBaJing Cosmic Ray Laboratory (Tibet, P.R. China, 4300 m a.s.l.). Its main fields of research include gamma-ray astronomy with an energy threshold of a few hundreds GeV and Cosmic Ray physics up to PeV energies. The ARGO-YBJ detector consists of a single layer of RPCs operated in streamer mode, housed in a large building of about 11,000 m2. The signals from each RPC are picked up by 80 readout strips 61.8 cm long and 6.75 cm wide (23 strips/m2) that allow the shower front reconstruction with a high space-time resolution. In order to fully investigate the PeV region, where the readout by strips saturates, an analog readout has been implemented by instrumenting each RPC with two large size electrodes of dimensions 1.23 × 1.39 m2. Since December 2009 the RPC charge readout has been in operation on the entire central carpet (about 5800 m2). The ARGO-YBJ detector equipped with the analog readout is able to measure the particle density from tens to many thousands of particles per m2. Here we describe in detail the analog readout of RPCs in ARGO-YBJ and discuss the performance of the system that implements it.

The ARGO-YBJ experiment has been in stable data taking since November 2007 at the YangBaJing Cosmic Ray Laboratory (Tibet,P.R. China, 4300 m a.s.l.). Its main fields of research are γ-astronomy with an energy threshold of a few hundred GeV and cosmic ray physics in the 1-1000 TeV energy range. The ARGO detector consists of a single layer of RPCs operated in streamer mode, covering a total instrumented area of about 10,000 m2. Signals from each RPC are picked up with 80 read-out strips 6.7 cm wide and 62 cm long (23 strips/m2) that allow the shower front reconstruction with an high space-time resolution. In order to fully investigate the PeV region, where the previous (digital) read-out saturates, an analog one has been implemented by instrumenting each RPC with two large size pads of dimension 1.39 × 1.23 m2. In this paper we describe the hardware solution that implements the real-time charge read-out in the ARGO-YBJ experiment, paying a special attention to the synchronization with the central data acquisition system, which also is described.

This paper summarizes the trends in device structures for low power (voltage) operation. Product driving forces and the expected evolution of standard CMOS are described to provide context for the presentation. Alternatives to CMOS to achieve enhanced performance-cost objectives include engineered CMOS, thin-film SOI, BiCMOS, and complementary GaAs. An assessment of the status, advantages, and limitations of each is offered. >