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Inductor is an essential component in Integrated Voltage Regulator(IVR) which is strongly corresponding to the efficiency of power management. In 2018 ECTC, an on-chip solenoid inductor package integrated with high-permeability magnetic(MAG) film and two ultra-thick Cu trace was successfully demonstrated, which exhibits the benefits of higher inductance, lower resistance, and competitive packaging dimension [1]. Two ultra-thick Cu trace for coils of inductor device inevitably accompanies with higher topography that will induce some concerns on processes, one of them is like bubble defect from spin coating process of photo resist. On the other hand, uneven plan resulted from high topography will also cause poor co-planarity(COP) post bump formation, result in concerns like cold joint in assembly process. In order to resolve this hindrance, a polish process on polymer and Cu by chemical & mechanistic planarization (CMP) is introduced to improve the topography of the inductor package. In the paper, a key process issue, interface delamination, relating to CMP will be disclosed. And the key approach that is how to optimize Cu surface treatment and parameter of CMP process for delamination improvement will be focused. In short, we face a critical issue poor COP post bump formation that induced from high topography in ultra-thick Cu scheme. How to realize CMP process for planarization is a key and must be relied on optimization of key approaches for delamination. At last, compared to the air-core thick copper inductor package reported last year, the results show that CMP can improved COP around 3~5-fold, and have comparable performance of electric resistance before/post wafer level torture.

Implementation of thick Cu inductor in IC chips has been a highly challenging task for Far-backend packaging industry. One of the major concerns is that the thicker Cu trace wrapped by re-passivation polymer layers (Polymer-1 & Polymer-2) is often accompanied by remarkable internal stress in the overall package, which is plagued with the risk of layer-to-layer delamination and/or interface micro-cracks. In this paper, a thick Cu inductor integrated with a WLCSP-like packaging solution is demonstrated for the first time through delamination improvement, which depends strongly on both (1) via-opening (etching) and (2) post top copper treatment processes in the specific scheme. In the via-opening (etching) process, an optimized etching method is proposed to minimize the surface roughness (Ra) of polymer-1 to 2~3 nm and concurrently achieve byproducts free. On the other hand, for the subsequent post top copper treatment processes, the introduced XYZ plasma and wet clean treatment are carried out to enhance the seed layer removal efficiency. As a result, the metal residue is substantially reduced to lower than 0.1% from 1.7% according to XPS analysis. The XYZ plasma treatment also benefits the surface roughness (Ra) of polymer-1 to around 30~35 nm, which is sufficient for later polymer-1 & -2 interface adhesion. These treatment approaches will be systematically presented and discussed in detail with experimental evidence. By means of the surface modification approaches reported in this study, the interface delamination phenomenon was greatly improved. The thicker Cu on-chip inductor embedded with WLCSP-like package successfully passed multi-reflow with 10 cycles and component level reliability tests, such as MSL1+HTS500hrs and MSL1+u-HAST96hrs. Meanwhile, compared to common planar spiral inductors fabricated by Fab process, not only was the inductance boosted, but the Cu trace resistance is also greatly reduced 10-fold. Moreover, the most striking feature of this packaging solution is that one can insert some novel high-permeability materials into this novel packaging scheme for much better electrical performance simply depending on customer requirements and designs.