158 results on '"Rooyackers, R."'
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2. Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets
3. Experimental analysis of differential pairs designed with line tunnel FET devices
4. Impact of the Zn diffusion process at the source side of InxGa1−xAs nTFETs on the analog parameters down to 10 K
5. Proton radiation effects on the self-aligned triple gate SOI p-type tunnel FET output characteristic
6. First demonstration of ∼3500 cm2/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack
7. Analysis of the transistor efficiency of gas phase Zn diffusion In0.53Ga0.47As nTFETs at different temperatures
8. Impact of InxGa1−x composition and source Zn diffusion temperature on intrinsic voltage gain in InGaAs TFETs
9. Top-down InGaAs nanowire and fin vertical FETs with record performance
10. Record mobility (μeff ∼3100 cm2/V-s) and reliability performance (Vov∼0.5V for 10yr operation) of In0.53Ga0.47As MOS devices using improved surface preparation and a novel interfacial layer
11. Beyond-Si materials and devices for more Moore and more than Moore applications
12. Comparative study of vertical GAA TFETs and GAA MOSFETs in function of the inversion coefficient
13. Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures
14. Influence of the Ge amount at source on transistor efficiency of vertical gate all around TFET for different conduction regimes
15. Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures
16. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices
17. Comparison between vertical silicon NW-TFET and NW-MOSFETfrom analog point of view
18. Study of low frequency noise in vertical NW-Tunnel FETs with different source compositions
19. Impact of the diameter of vertical nanowire-tunnel FETs with Si and SiGe source composition on analog parameters
20. Perspective of tunnel-FET for future low-power technology nodes
21. A New Direction for III–V FETs for Mobile CPU Operation Including Burst-Mode: In0.35Ga0.65As Channel.
22. In0.53Ga0.47As quantum-well MOSFET with source/drain regrowth for low power logic applications
23. Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature
24. Unity gain frequency on FinFET and TFET devices
25. A new complementary hetero-junction vertical Tunnel-FET integration scheme
26. Back bias influence on analog performance of pTFET
27. NW-TFET analog performance for different Ge source compositions
28. Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures.
29. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices.
30. Experimental analog performance of pTFETs as a function of temperature
31. Trap-Assisted Tunneling in Vertical Si and SiGe Hetero-Tunnel-FETs
32. Advancing CMOS beyond the Si roadmap with Ge and III/V devices
33. Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors
34. Electrical results of vertical Si N-Tunnel FETs
35. Si-based tunnel field-effect transistors for low-power nano-electronics
36. Record low contact resistivity to n-type Ge for CMOS and memory applications
37. Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions
38. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?
39. The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET
40. Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices
41. First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling
42. Impact of Strain on ESD Robustness of FinFET Devices
43. Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
44. Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs
45. A 10-Bit current-steering FinFET D/A converter
46. Influence of temperature on the operation of strained triple-gate FinFETs
47. Comparison of scaled floating body RAM architectures
48. Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs
49. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
50. Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization
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