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Historically, obtaining efficient coupling from single-mode waveguides in high performance GaAs modulator devices to single-mode fiber has been difficult. The reasons are; (1) the large modal mismatch between the elliptical waveguide output and the gaussian profile of the optical fiber; and (2) the large NA difference (0.9 for the waveguide in one direction) and 0.16 for fiber. Despite this difficulty, there exists a need for packaging devices with multiple fiber outputs, that have been gang-aligned, efficiently coupled, and hermetically sealed. (The latter item will be very important in automotive or aerospace applications.) Instead of trying to have fiber penetrate the package wall, the SNL approach to efficient coupling and hermeticity has been to allow light to penetrate the package wall. This has been accomplished by sending out the light normal to the waveguides and collecting it with a binary optic that focuses it on to a fiber outside the package. The optical design of this system requires that the beam be nearly collimated as it leaves the surface of the device. To accomplish this, a second-order grating was etched into a 200 /spl mu/m long section of an adiabatically expanded single-mode waveguide. >

Many of the potential applications for parallel photonic data links could benefit from a bi-directional Optoelectronic Multi-Chip Module (OEMCM), where the optical transmitter, receiver, and first-level interface electronics are combined into a single package. It would be desirable for such a module to exhibit low power consumption, have a simple electronic interface that can operate at a variety of speeds and possess a capability to use interchangeable optics for a variety of external connections. Here, we describe initial results for a parallel photonic link technology that exhibits those properties. This link uses high-efficiency, back-emitting, two-dimensional Vertical Cavity Surface-Emitting Laser (VCSEL) arrays operating at 980 nm. The lasers are matched, via integrated microlenses, to corresponding monolithically-integrated photoreceiver arrays that are constructed in a InGaAs/InP Heterojunction Bipolar Transistor (HBT) technology. In initial breadboard-level tests, the photonic data channels built with these devices have been demonstrated with direct (3.3 V) CMOS drive of the VCSELs and a corresponding CMOS interface at the photoreceiver outputs. These links have shown electrical power consumption as low as 42 mW per channel for a 50% average duty cycle while operating at 100 Mb/s.

An ultra-low-power, long-wavelength photoreceiver based on InGaAs-InP heterojunction bipolar transistors is reported. The photoreceivers were designed for massively parallel applications where low-power density is necessary for both electrical and thermal reasons. We demonstrate two-dimensional, four-by-four arrays of photoreceivers for free-space optical data links that interface directly with 3.3 V CMOS ASICs and dissipate less than 12 mW/channel; lower power is possible. Propagation delays of /spl sim/1 nsec were measured and large signal operation to 800 Mbits/sec is demonstrated. The array is on a 500 /spl mu/m pitch and can be easily scaled to much higher density. The photoreceivers can be utilized in both free-space and guided-wave applications.

The device designs used for this work are based on highly efficient vertical-cavity surface emitting lasers, connected to corresponding photoreceivers. In order to meet the constraints of packaging, the optical system used in the design is implemented by the integration of microlenses into the laser and photoreceiver substrates.

New applications of photonic interconnects will involve the insertion of parallel-channel links into Multi-Chip Modules (MCMs). Such applications will drive photonic link components into more compact forms that consume far less power than traditional telecommunication data links. MCM-based applications will also require simplified drive circuitry, lower cost, and higher reliability than has been demonstrated currently in photonic and optoelectronic technologies. The work described is a parallel link array, designed for vertical (Z-Axis) interconnection of the layers in a MCM-based signal processor stack, operating at a data rate of 100 Mb/s. This interconnect is based upon high-efficiency VCSELs, HBT photoreceivers, integrated micro-optics, and MCM-compatible packaging techniques.

Low-power photoreceivers based on InGaAs/InP heterojunction bipolar transistors (HBTs) and p-i-n diodes for highly-parallel optical data links have been designed, fabricated and characterized. The receivers are designed to operate from 980 nm to over 1.3 /spl mu/m and interface directly with 3.3 V CMOS. SPICE was utilized to investigate circuit topographies that minimize power dissipation while maintaining large signal operation required to interface directly with CMOS. Low-power dissipation of /spl sim/10 mW/channel has been achieved at bit rates up to 800 Mbits/sec. Performance characteristics of discrete HBTs and of low-power photoreceivers fabricated with p-i-n/HBT circuits are reported.