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Quanvolutional neural networks (QNNs) have been successful in image classification, exploiting inherent quantum capabilities to improve performance of traditional convolution. Unfortunately, the qubit's reliability can be a significant issue for QNNs inference, since its logical state can be altered by both intrinsic noise and by the interaction with natural radiation. In this article, we aim at investigating the propagation of logical-shift errors (i.e., the unexpected modification of the qubit state) in QNNs. We propose a bottom–up evaluation reporting data from 13 322 547 200 logical-shift injections. We characterize the error propagation in the quantum circuit implementing a single convolution and then in various designs of the same QNN, varying the dataset and the network depth. We track the logical-shift error propagation through the qubits, channels, and subgrids, identifying the faults that are more likely to cause misclassifications. We found that up to 10% of the injections in the quanvolutional layer cause misclassification and even logical-shifts of small magnitude can be sufficient to disturb the network functionality. Our detailed analysis shows that corruptions in the qubits' state that alter their probability amplitude are more critical than the ones altering their phase, that some object classes are more likely than others to be corrupted, that the criticality of subgrids depends on the dataset, and that the control qubits, once corrupted, are more likely to modify the QNN output than the target qubits.

Traditional multiple access schemes, as well as more recent preamble-based schemes, cannot achieve the extremely low latency, complexity, and collision probability required by the next-generation Internet-of-Things (IoT) networks to operate. To address such issues and further reduce the latency and packet loss, we introduce a novel semi-grant-free multiple access protocol for short packet transmission, the partial-information multiple access (PIMA) scheme. PIMA transmissions are organized in frames, and in the partial information acquisition (PIA) sub-frame of each frame, the base station (BS) estimates the number of active devices, i.e., the devices having packets waiting for transmission in their queue. Based on this estimate, the BS chooses both the total number of slots to be allocated in the data transmission (DT) sub-frame and the respective user-to-slot assignment. Although collisions may still occur due to multiple users assigned to the same slot, they are drastically reduced with respect to slotted ALOHA-based schemes, while achieving lower latency than both time-division multiple-access (TDMA) and preamble-based protocols, due to the extremely reduced overhead of the PIA sub-frame. We assess the performance of PIMA under various activation statistics, proving the robustness of the proposed solution to the traffic intensity, also with traffic bursts.

Most permissionless blockchains inherently suffer from throughput limitations. Layer-2 systems, such as side-chains or Rollups, have been proposed as a possible strategy to overcome this limitation. Layer-2 systems interact with the main-chain in two ways. First, users can move funds from/to the main-chain to/from the layer-2. Second, layer-2 systems periodically synchronize with the main-chain to keep some form of log of their activity on the main-chain - this log is key for security. Due to this interaction with the main-chain, which is necessary and recurrent, layer-2 systems impose some load on the main-chain. The impact of such load on the main-chain has been, so far, poorly understood. In addition to that, layer-2 approaches typically sacrifice decentralization and security in favor of higher throughput. This paper presents an experimental study that analyzes the current state of Ethereum layer-2 projects. Our goal is to assess the load they impose on Ethereum and to understand their scalability potential in the long-run. Our analysis shows that the impact of any given layer-2 on the main-chain is the result of both technical aspects (how state is logged on the main-chain) and user behavior (how often users decide to transfer funds between the layer-2 and the main-chain). Based on our observations, we infer that without efficient mechanisms that allow users to transfer funds in a secure and fast manner directly from one layer-2 project to another, current layer-2 systems will not be able to scale Ethereum effectively, regardless of their technical solutions. Furthermore, from our results, we conclude that the layer-2 systems that offer similar security guarantees as Ethereum have limited scalability potential, while approaches that offer better performance, sacrifice security and lead to an increase in centralization which runs against the end-goals of permissionless blockchains.

Fifth-generation (and beyond) networks are characterized by ever more demanding requirements in terms of speed, bandwidth, and number of servable users. Fast and reliable access to the main network is mandatory, requiring technologies and procedures that ensure high performing cell search and initial access (IA). Existing phased array antennas (PAAs) are limited by the single beam scanning approach and complex feeding systems. In this paper, a beamforming metasurface that shifts the field manipulation from an electric level to an electromagnetic one is proposed for speeding up the IA procedure with respect to a traditional system using PAAs. The main advantage is given by the simultaneous transmission of multiple signals in different directions. The numerical results demonstrate that a much faster IA with similar success probability can be reached. Our system provides high gain, parallel computation, and scalability for larger systems, becoming a relevant candidate in the new radio and smart electromagnetic environment context.

Time-resolved imaging by means of single-photon avalanche diodes (SPADs) has achieved widespread interest in recent years, especially since technological progress has opened the way to the development of multichannel time-correlated single-photon counting (TCSPC) acquisition systems. Unfortunately, currently available TCSPC imagers feature relatively low performance with respect to state-of-the-art single-channel systems. A real breakthrough in this field would be the exploitation of large arrays of high-performance SPAD detectors developed by means of dedicated fabrication processes, usually referred to as custom technology. Custom-technology SPADs require external electronics potentially leading to interconnection issues for densely integrated arrays. In this paper, we present a new fully integrated front-end circuit able to provide both quenching/reset and timing functionalities while requiring a single connection toward the SPAD. This is the first fully integrated circuit reported in literature that can provide both the timing information about the photon time of arrival with a jitter as low as 37 ps and apply high-voltage pulses up to 50 V in order to meet the requirements of several detectors, including the new red-enhanced SPAD. Combining these two capabilities in a single circuit strongly reduces the complexity of the connection between an array of custom-technology SPADs and the relative external front end, thus paving the way for the exploitation of high-performance SPADs in TCSPC imaging systems.

In recent years, time-correlated single photon counting (TCSPC) has become the technique of choice in many life science analyses, where fast and faint luminous signals are recorded with picosecond accuracy. Nevertheless, the maximum operating frequency of a single TCSPC acquisition channel limits the measurement speed, especially when scanning point systems are exploited. In order to increase the speed of TCSPC experiments, many multichannel systems based on single photon avalanche diode arrays have been proposed in the literature, which integrate thousands of pixels on the same chip. Unfortunately, the huge number of data generated by this kind of system can easily bring to the saturation of the transfer bandwidth to the external processing unit. For this reason, several different readout architectures have been proposed in the literature, attempting to exploit at best the limited bandwidth under TCSPC operating conditions. In this paper, some typical readout approaches, namely clock-driven and event-driven readouts, are discussed and compared, along with a recently-introduced router-based algorithm that is specifically designed to obtain maximum bandwidth exploitation under any condition. Quantitative comparisons are performed starting from imager response of the systems, which is the rate of recorded events in the case of uniform illumination of the detector array.

Single-photon detectors play a key role in many research fields such as biology, chemistry, medicine, and space technology, and in recent years, single-photon avalanche diodes (SPADs) have become a valid alternative to photo multiplier tubes (PMTs). Moreover, scientific research has recently focused on single-photon detector arrays, pushed by a growing demand for multichannel systems. In this scenario, we developed a compact 32-channel system for time-resolved single-photon counting applications. The system is divided into two independent modules: a photon detection head including a 32 × 1 SPAD array built in custom technology, featuring high time resolution, high photon detection efficiency (44% at 550 nm), and low dark count rate (mean value

Convolutional neural networks (CNNs) are becoming attractive alternatives to traditional image-processing algorithms in self-driving vehicles for automotive, military, and aerospace applications. The high computational demand of state-of-the-art CNN architectures requires the use of hardware acceleration on parallel devices. Field-programmable gate arrays (FPGAs) offer a great level of design flexibility, low power consumption, and are relatively low cost, which make them very good candidates for efficiently accelerating neural networks. Unfortunately, the configuration memories of SRAM-based FPGAs are sensitive to radiation-induced errors, which can compromise the circuit implemented on the programmable fabric and the overall reliability of the system. Through neutron beam experiments, we evaluate how lossless quantization processes and subsequent data precision reduction impact the area, performance, radiation sensitivity, and failure rate of neural networks on FPGAs. Our results show that an 8-bit integer design can deliver over six times more fault-free executions than a 32-bit floating-point implementation. Moreover, we discuss the tradeoffs associated with varying degrees of parallelism in a neural network accelerator. We show that, although increased parallelism increases radiation sensitivity, the performance gains generally outweigh it in terms of global failure rate. [ABSTRACT FROM AUTHOR]

Convolutional neural networks are quickly becoming viable solutions for self-driving vehicles, military, and aerospace applications. At the same time, due to their high level of design flexibility, reprogrammable capability, low power consumption, and relatively low cost, the field-programmable gate arrays (FPGAs) are very good candidates to implement the neural networks. Unfortunately, the radiation-induced errors are known to be an issue in static random-access memory (SRAM)-based FPGAs. More specifically, we have seen that particles can change the content of the FPGA’s configuration memory, consequently corrupting the implemented circuit and generating the observable errors at the output. Through extensive fault injection, we determine the reliability impact of applying binary quantization to the convolutional layers of neural networks on FPGAs, by analyzing the relationships between model accuracy, resource utilization, performance, error criticality, and radiation cross section. We were able to find that a design with quantized convolutional layers can be 39% less sensitive to radiation, whereas the portion of errors that are considered critical (misclassifications) in the network is increased by 12%. Moreover, we also derive generic equations that consider both accuracy and radiation in order to model the overall failure rate of neural networks. [ABSTRACT FROM AUTHOR]

Neural networks are becoming an attractive solution for automatizing vehicles in the automotive, military, and aerospace markets. Thanks to their low-cost, low-power consumption, and flexibility, field-programmable gate arrays (FPGAs) are among the promising devices to implement neural networks. Unfortunately, FPGAs are also known to be susceptible to radiation-induced errors. In this paper, we evaluate the effects of radiation-induced errors in the output correctness of two neural networks [Iris Flower artificial neural network (ANN) and Modified National Institute of Standards and Technology (MNIST) convolutional neural network (CNN)] implemented in static random-access memory-based FPGAs. In particular, we notice that radiation can induce errors that modify the output of the network with or without affecting the neural network’s functionality. We call the former critical errors and the latter tolerable errors. Through exhaustive fault injection, we identify the portions of Iris Flower ANN and MNIST CNN implementation on FPGAs that are more likely, once corrupted, to generate a critical or a tolerable error. Based on this analysis, we propose a selective hardening strategy that triplicates only the most vulnerable layers of the neural network. With neutron radiation testing, our selective hardening solution was able to mask 40% of faults with a marginal 8% overhead in one of our tested neural networks. [ABSTRACT FROM AUTHOR]

In this paper, we experimentally and analytically evaluate the reliability of two state-of-the-art neural networks for linear regression and pattern recognition (multilayer perceptron and single-layer perceptron) implemented in a system-on-chip composed of a field-programmable gate array (FPGA) and a microprocessor. We have considered, for each neural network, three different activation function complexities, to evaluate how the implementation affects FPGAs reliability. As we show in this paper, higher complexity increases the exposed area but reduces the probability of one failure to impact the network output. In addition, we propose to distinguish between critical and tolerable errors in artificial neural networks. Experiments using a controlled heavy-ions beam show that, for both networks, only about 30% of the observed output errors actually affect the outputs correctness. We identify the causes of critical errors through fault injection, and found that faults in initial layers are more likely to significantly affect the output. [ABSTRACT FROM PUBLISHER]

Thanks to the capability of efficiently executing massive computations in parallel, general purpose graphic processing units (GPGPUs) have begun to be preferred to CPUs for several parallel applications in different domains. Two are the most relevant fields in which, recently, GPGPUs have begun to be employed: high performance computing (HPC) and embedded systems. The reliability requirements are different in these two applications domain. In order to be employed in safety-critical applications, GPGPUs for embedded systems must be qualified as reliable. In this paper, we analyze through neutron irradiation typical parallel algorithms for embedded GPGPUs and we evaluate their reliability. We analyze how caches and threads distributions affect the GPGPU reliability. The data have been acquired through neutron test experiments, performed at the VESUVIO neutron facility at ISIS. The obtained experimental results show that, if the L1 cache of the considered GPGPU is disabled, the algorithm execution is most reliable. Moreover, it is demonstrated that during a FFT execution most errors appear in the stages in which the GPGPU is completely loaded as the number of instantiated parallel tasks is higher. [ABSTRACT FROM PUBLISHER]

A higher Degree of Parallelism decreases the code execution time. However, a higher scheduler strain is necessary to manage the increased number of parallel processes, which have the countermeasure of increasing the graphics processing unit (GPU) cross section. This hypothesis is confirmed by extensive neutron irradiation testing to study how the Degree of Parallelism affects GPU reliability. Moreover, the cache distribution forced by different Degrees of Parallelism is proved to influence the application error rate. Finally, the Mean Executions Between Failures metric is introduced to evaluate the amount of data computed correctly by the GPU on a practical application. [ABSTRACT FROM PUBLISHER]

In this paper we assess the neutron sensitivity of Graphics Processing Units (GPUs) when executing a Fast Fourier Transform (FFT) algorithm, and propose specific software-based hardening strategies to reduce its failure rate. Our research is motivated by experimental results with an unhardened FFT that demonstrate a majority of multiple errors in the output in the case of failures, which are caused by data dependencies. In addition, the use of the built-in error-correction code (ECC) showed a large overhead, and proved to be insufficient to provide high reliability. Experimental results with the hardened algorithm show a two orders of magnitude failure rate improvement over the original algorithm (one order of magnitude over ECC) and an overhead 64% smaller than ECC. [ABSTRACT FROM PUBLISHER]

Single Event Burnout and Gate Rupture are catastrophic failures due to cosmic rays that can occur simultaneously. It is shown that negatively biasing the gate leads to a substantial increase of SEB cross section in particular when the collector voltage is closer to the safe operating area of the device. [ABSTRACT FROM PUBLISHER]

Neutron radiation experiment results on matrix multiplication on graphic processing units (GPUs) show that multiple errors are detected at the output in more than 50% of the cases. In the presence of multiple errors, the available hardening strategies may become ineffective or inefficient. Analyzing radiation-induced error distributions, we developed an optimized and experimentally tuned software-based hardening strategy for GPUs. With fault-injection simulations, we compare the performance and correcting capabilities of the proposed technique with the available ones. [ABSTRACT FROM AUTHOR]

We investigate the occurrence of Multiple Bit Upsets in commercial SRAMs of 4 Mbits and 32 Mbits when irradiated with neutrons. The devices were irradiated at TSL facility with QMN beams of energies from 50 MeV to 180 MeV. Experimental data demonstrate that the dynamic-stress increases SRAMs sensitivity as well as MBUs occurrence for both the memory types. We also show that both SEU and MBU cross section may depend on memory architecture and memory utilization. [ABSTRACT FROM AUTHOR]

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RAL-ISIS facility. The ISIS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 108 in the energy range 19-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications. [ABSTRACT FROM AUTHOR]