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Embedded computer vision systems are increasingly being adopted across various domains, playing a pivotal role in enabling advanced technologies such as autonomous vehicles and industrial automation. Their cost-effectiveness, compact size, and portability make them particularly well-suited for diverse implementations and operations. In real-time scenarios, these systems must process visual data with minimal latency, which is crucial for immediate decision-making. However, these solutions continue to face significant challenges related to computational efficiency, memory usage, and accuracy. This research addresses these challenges by enhancing classification methodologies, specifically in Gray Level Co-occurrence Matrix (GLCM) feature extraction and Support Vector Machine (SVM) classifiers. To maintain a high level of accuracy while preserving performance, a smaller feature set is selected following a comprehensive complexity analysis and is further refined through Correlation-based Feature Selection (CFS). The proposed method achieves an overall classification accuracy of 84.76% with a feature set reduced by 79.2%, resulting in a 72.45% decrease in processing time, a 50% reduction in storage requirements, and up to a 77.8% decrease in memory demand during prediction. These improvements demonstrate the effectiveness of the proposed approach in improving the adaptability and capabilities of embedded vision systems (EVS), optimizing their performance under the constraints of real-time limited-resource environments.

This study presents an innovative control method for a specific type of DC/DC power converter, known as a three-leg interleaved non-isolated converter (IBC), which is particularly useful for proton exchange membrane fuel cell (PEMFC) electric vehicles (EVs). The control strategy introduced is a dual-loop system, utilizing a fractional-order proportional-integral (FOPI) technique. This includes two components: an external loop for DC bus voltage regulation and an internal one for current control(control of the FC through their IBC). This approach aims to swiftly adjust to changes in load and disturbances while maintaining high-quality dynamic performance, even in open circuit faults (OCF) scenarios. The FOPI based-controller’s optimal parameters are meticulously determined through the Equilibrium Optimizer (EO) algorithm, enhancing overall system performance and responsiveness. Evaluation and comparison of the proposed controller’s efficiency and superior performance are conducted against formal FOPI and other optimization algorithms using Matlab-Simulink simulation software. Practical validation involves the implementation of the proposed controller on a laboratory prototype-a 1.2KW three-phase interleaved boost converter-controlled by a dSPACE 1104 accusation card. The method exhibits outstanding practical results across diverse tests, including load variations, steady and transient states, and OCF modes. This comprehensive study contributes valuable insights into the realm of DC/DC power converter control.

In today’s interconnected world, with the changes caused by the technological revolution conflicts, politics, diseases and climate changes, along with the growing influence of artificial intelligence (AI), the threat of manipulating data is on the rise. In the field of satellite imagery, data transfer security is especially crucial. One of the most important tools for safeguarding satellite images during storage and transmission is cryptography. It offers an imperceptible substitute to quick response codes. The literature focuses predominantly on software implementations of encryption techniques, despite scenarios where hardware cryptographic solutions are preferable or necessary due to increased requirements for speed, power, or data security. IP cores offer a versatile and widely applicable solution for hardware development, serving as the basic building blocks for constructing processors on field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). This paper presents an innovative embedded chaotic algorithm designed to enhance the security of satellite images by integrating Ribonucleic Acid (RNA)-encoded encryption, Fisher-Yates shuffling and the Fractional order 4D Chen system. To achieve an optimal balance between encryption time and security, the original image undergoes strategic block division, with each block undergoing encryption via a series of steps including XOR operations, RNA dynamic encoding and decoding, RNA dynamic operation rules, and Fisher-Yates shuffle. The primary objective of this study is to enhance the efficiency and speed of the encryption process by presenting the realisation of a robust cryptographic scheme in the form of an IP core tailored which has been implemented on ZedBoard FPGA using the Vivado High-Level Synthesis (HLS) design suite. By utilising the hardware parallelism intrinsic to FPGA architectures, we attain significant enhancements in execution time compared to the software-based implementation (frequency of 160.01 MHz). Experimental and analytical results demonstrate the algorithm’s robust security, resilience to single-event upsets, large key space, and low time complexity.

This study introduces a novel approach to enhance state and unknown input estimation for the synchronous reluctance motor, utilizing the Takagi-Sugeno fuzzy representation. A proportional multi-integral observer structure is introduced, capable of capturing a wider range of unknown input dynamics compared to the previous proportional integral observer utilized in prior research. Stability conditions, obtained using the quadratic Lyapunov function, are formulated as linear matrix inequalities to guarantee the asymptotic convergence of the estimation error. To evaluate the effectiveness of the proposed observer, different cases were considered, including scenarios with slow and fast variations of the unknown input. Through hardware-in-the-loop validation, the results clearly demonstrate the superiority of the proposed method over the earlier approach. This advancement signifies a significant improvement in the estimation accuracy and reliability of the Synchronous Reluctance Motor.

Generative text summarization can condense large volumes of information into a concise summary. It helps users quickly grasp the main points of a text without having to read the entire document. Machine learning (ML) plays a pivotal role in this domain, offering significant advantages in information processing and comprehension. In this paper we present CoMod, an abstractive method for generating the context of a document, from its content and that of the referenced documents, if any. CoMod analyzes the intricate patterns and relationships within a document’s content, thereby extracting and inferring the underlying context. The context generation process involves using a word linearization process as well as a Markov model, specifically a Bigram model, to predict the likelihood of word sequences. The Markov model is trained on a corpus of text and used to generate coherent sentences based on the probabilities of transitioning from one word to another. Markov tables allows to adapt the generated context to a specific domain and can be built on the fly in CoMod. The approach was compared to other methods and demonstrated very encouraging capabilities by outperforming other approaches tested on the same datasets. It thus confirms the potential of generative methods in the field of automatic text summarization and their ability of leveraging the power of machine learning for context generation to revolutionize information management, boosting productivity, scalability and knowledge discovery in various domains.

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

Cardiovascular diseases are considered the number one cause of death across the globe which can be primarily identified by the abnormal heart rhythms of the patients. By generating electrocardiogram (ECG) signals, wearable Internet of Things (IoT) devices can consistently track the patient’s heart rhythms. Although Cloud-based approaches for ECG analysis can achieve some levels of accuracy, they still have some limitations, such as high latency. Conversely, the Fog computing infrastructure is more powerful than edge devices but less capable than Cloud computing for executing compositionally intensive data analytic software. The Fog infrastructure can consist of Fog-based gateways directly connected with the wearable devices to offer many advanced benefits, including low latency and high quality of services. To address these issues, a modular one-dimensional convolution neural network (1D-CNN) approach is proposed in this work. The inference module of the proposed approach is deployable over the Fog infrastructure for analysing the ECG signals and initiating the emergency countermeasures within a minimum delay, whereas its training module is executable on the computationally enriched Cloud data centers. The proposed approach achieves the F1-measure score ≈1 on the MIT-BIH Arrhythmia database when applying GridSearch algorithm with the cross-validation method. This approach has also been implemented on a single-board computer and Google Colab-based hybrid Fog-Cloud infrastructure and embodied to a remote patient monitoring system that shows 25% improvement in the overall response time.

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies ( $V_{dd}$ and $V_{dd}$ /2). The result of extensive HSPICE simulations regarding PVT (Process, Voltage, and Temperatures) variations and Noise Immunity Curve (NIC) show the improvements of the proposed designs up to 25% in transistors count and up to 98% in energy consumption reductions. Further, increasing the robustness of process variations and the noise tolerance compared to recent similar designs.

A Quranic optical character recognition (OCR) system based on convolutional neural network (CNN) followed by recurrent neural network (RNN) is introduced in this work. Six deep learning models are built to study the effect of different representations of the input and output, and the accuracy and performance of the models, and compare long short-term memory (LSTM) and gated recurrent unit (GRU). A new Quranic OCR dataset is developed based on the most famous printed version of the Holy Quran (Mushaf Al-Madinah), and a page and line-text image with the corresponding labels is prepared. This work’s contribution is a Quranic OCR model capable of recognizing the Quranic image’s diacritic text. A better performance in word recognition rate (WRR) and character recognition rate (CRR) is achieved in the experiments. The LSTM and GRU are compared in the Arabic text recognition domain. In addition, a public database is built for research purposes in Arabic text recognition that contains the diacritics and the Uthmanic script, and is large enough to be used with the deep learning models. The outcome of this work shows that the proposed system obtains an accuracy of 98% on the validation data, and a WRR of 95% and a CRR of 99% in the test dataset.

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary NAND (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (Vdd and Vdd/2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively.

This paper presents a comprehensive study of the impact of resistive harmonic loading on the design of integrated Class-F power amplifiers (PAs). The proposed time-domain waveform-based analysis allows for an evaluation of the performance of Class-F PAs while controlling both second and third harmonics simultaneously. The voltage mapping is presented to include the impact of the resistive second harmonic impedance in the design of Class-F PAs. Besides, drain current formulations as a function of conduction angle are used to evaluate the harmonic coefficients under the impact of resistive third harmonic impedance. As such, the combination of resistive second and third harmonics is modeled to study its impact on efficiency and optimum impedance in the Class-F PAs. For practical validation, the derived knowledge is applied to propose a novel integrated Class-F PA that absorbs the output capacitance into the match while maintaining a purely resistive load at the fundamental frequency. The output match is fabricated on a highly integrated NXP Laterally Diffused MOSFET (LDMOS) process. At 1.8 GHz, using NXP 5-mm LDMOS die, the integrated Class-F achieves a drain efficiency ranging from 52% to 61% at 5-W output power based on two different design topologies. Both prototypes demonstrate excellent isolation at the second and third harmonics. Measurement results confirm the theoretical framework reported in this paper.