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Your search keyword '"Rajamani, S."' showing total 11 results

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11 results on '"Rajamani, S."'

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1. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

2. Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

3. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

6. Simulation study of the electrophysiological mechanisms for heart failure phenotype.

11. Simulations of Ge based optically controlled field effect transistors

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