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A ultra-high purity carbon nanotube formulation and film is described. This material system has been successfully integrated into a semiconductor fabrication process for electronic device applications. Key challenges that were resolved to successfully implement this new material system into the semiconductor process are described.

In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.

This paper discusses the Elmore delay optimization technique by varying the wire width. It also throws a light on various aspects which affects the interconnect delay. We will see that the delay minimization to zero will lead to a larger area covering interconnect wires, which will ultimately increase the area cost of IC. So 10 to 15% delay will give a good result keeping the IC size also in control. Optimization techniques if applied in IC designing, optimizes various other factors like the power dissipation and also the circuit compactness. So a good and robust optimization technique is required. In our work, we have employed the Convex Optimization Technique as it has the ability for finding the global optimum to a problem under any constraints with a less computational complexity.

In the field of electronic design automation physical design of integrated circuits is one of the most interesting and challenging areas. During physical design, all design components are instantiated with their geometric representations and directly impacts circuit performance, area, reliability, power, and manufacturing yield. Due to its high complexity, physical design is split into several key steps. One of the vital stages of Physical Design is Partitioning in which a circuit is broken up into smaller sub-circuits or modules which can each be designed or analyzed individually, subject to design constraints such as maximum partition sizes and maximum path delay. In this paper, we study about the various heuristic approaches towards the circuit partitioning problems. We have also given a comparative analysis of different algorithms which have been proposed so far in solving this partitioning problem.

As an intermediate between discrete molecules and bulk materials, carbon nanotubes (CNTs) require a prescribed mix of processing tactics to scalably transform them from a heterogeneous blend of metal catalysts, amorphous carbons and CNTs into a robust colloidal formulation suitable for spin-on semiconductor applications such as non-volatile memory. In this manuscript, we will show historical quality control (QC) data collected over a four year period on three sequential generations of a single formulation. Results from this data will show that using our controlled processing methods, we can reproducibly prepare liter-scale quantities of spin-on CNTs formulations, meeting quality specifications expected for other electronics-grade thin-film precursors. Presented QC data will highlight our continuous improvement efforts in trace-metal (TM) control which has ultimately allowed us to reduce our process mean from ~40 ppbw total TM to less than 3 ppbw. QC defectivity data gathered from electron and optical microscopy will also be presented on each formulation generation, along with a description of the defect taxonomy developed which has help reduce defectivity in future formulations.