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Half Bridge Modular Multilevel Converter (HB-MMC), a sub-module of modular multilevel converter (MMC), is widely accepted voltage source converter (VSC) topology for high voltage DC (HVDC) systems. HB-MMC has a disadvantage that it did not limit, clear DC fault current and protect IGBT converter from damage. For confining DC fault current, it is necessary to place fault current limiter (FCL) in series with HB-MMC. In this paper, Author presents two novel fault current limiter i.e. IGBT based fault current limiter (IGBT-FCL) and Parallel RL fault current limiter. IGBT based FCL consists of IGBTs and diode which are connected in parallel to each other. IGBT based FCL perform two functions i.e. it circumscribe large DC fault current and also clear DC fault current. The RL circuit has connected in series with HB-MMC. Due to no zero crossing point in DC systems, Hybrid DC circuit breaker (HDCCB) has been connected in series with Parallel RL and HB-MMC to clear the fault instantly. IGBT based FCL confine the fault current to 4 kA from 14 kA which is 72% reduction in fault current and clear fault current within 14 ms. The parallel RL circuit confines the fault current to 3.6 kA from 14 kA which shows 75% suppression of maximum DC fault current. With the help of HDCCB, the fault is cleared within 18 ms. The PSCAD/EMTDC has been used for designing of HB-MMC, IGBT-FCL, Parallel RL circuit and HDCCB.

A vector strategy for controlling a three-phase shunt active filter (SAPF), which is connected to the network with the existing nonlinear load, is proposed. The filter consists of a semiconductor voltage inverter with fully controlled switches, a capacitive storage and a single-link RL filter. The DC voltage stabilization of the capacitive storage using a second-order sliding mode, which is based on the implementation of a finite twisting algorithm is performed. A vector algorithm (the "rhombus-type") for tracking the instantaneous value of the current to generate a compensating current is used. The proposed algorithm uses the methods of projective geometry to determine the relative position of the space vectors of the voltages and the currents of the power supply system, so it does not contain difficult mathematical operations (for ex. - calculating inverse trigonometric functions). The choice of the appropriate output voltage vector of the SAPF inverter is based on the spatial location of the equivalent control vector, the coordinates of which are calculated in real time. The current tracking error sign is estimated using a quasi-stationary two-dimensional sliding surface, which is a linear combination of the components of the two-dimensional current error vector of the RL filter. A simulation model is developed and the results of simulation are analyzed. The proposed strategy is compared with the traditional hysteresis algorithm according to the criteria of the number of switchings and the coefficient of harmonic distortion in the current consumed from the network.

A simplified vector strategy for tracking the compensation current of a three-phase shunt active filter (SAPF) is proposed. SAPF consists of a semiconductor voltage inverter with fully controlled switches, a capacitive storage and a single-link RL filter. The difference in the speed of the dynamic system allows us to distinguish between a fast subsystem, in which the vector method of current control is actually used, and a slow subsystem, the function of which is to stabilize the constant voltage of the storage capacitor. The DC voltage of this capacitor is stabilized by a second-order sliding mode using a finite double-twisting algorithm. The first-order two-dimensional sliding mode is used to tracking the compensation current. The proposed algorithm uses the methods of projective geometry to unambiguously determine the mutual location of spatial vectors of voltages and errors of power supply currents. Since the algorithm does not have difficult mathematical operations for calculating inverse trigonometric functions, it is quite simple in technical implementation. The components of the space vector of equivalent control in a stationary coordinate system are calculated in real time. The choice of the desired output voltage vector of the SAPF inverter is determined by the location of the vector of equivalent control relative to the set of these stationary vectors. Estimation of signs of components of a two-dimensional vector of an error of tracking of current occurs with use of a quasi-stationary two-dimensional sliding surface. The algorithm uses the figure of permissible errors in the form of a circle with a radius equal to the desired value of the instantaneous deviation of each component of the stum from the reference value. A simulation model is built and the simulation results are analyzed.

The paper introduces the control and operation of a grid-connected converter with an energy storage system. A complete mathematical model is presented for a converter and its control. The system under study is a small microgrid comprising an AC grid that is feeding a DC load through a converter. The converter is connected to the AC grid through R-L filter. On the DC side an energy storage system ESS is connected to the DC bus. Classical linear controllers have limitations due to their slow transient performance and low robustness against parameter variations and load disturbances. In this paper, a machine learned controllers are used to deal with those drawbacks of the traditional controller. First, a study for conventional nested loop Proportional Integral for both outer and inner loops PI-PI controller is introduced. Then, a Data Driven Online Learning (DDOL) controller is proposed. This controller is a Proportional Integral Neural Network (PI-NN) that is used to enhance the system performance in terms of dynamic and steady-state responses. A comparison between the normal traditional PI-PI controller and the proposed DDOL ones is made under different operating scenarios. The converter control is tested under different operational conditions, and its dynamic and steady-state behavior is analyzed. The model is done through a MATLAB Simulink to check the normal operation of the network in a grid-connected mode under different load disturbances and AC input voltage. The results are showing that the intelligent controller can achieve the set reference points with better performance in terms of both dynamic and steady-state responses.

Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines.

A simple vector strategy for controlling the compensation current of a three-phase shunt active power filter (SAPF), which is based on the forced introduction of a first-order sliding mode is proposed. SAPF consists of a semiconductor voltage inverter with fully controlled switches, a capacitive storage and a single-link RL filter. Decomposition of the object of study according to the moving rates of the dynamic system allows to distinguish a fast subsystem that implements the vector method of controlling the compensation current, and a slow subsystem, the function of which is to stabilize the constant voltage of the drive capacitor. The DC voltage stabilization of the capacitive storage is performed using a finite twisting algorithm, which belongs to the class of the second order sliding modes. The first-order two-dimensional sliding mode to generate the compensation current is used. The proposed algorithm is a vector-type algorithm and uses the methods of projective geometry to unambiguously determine the mutual location of spatial vectors of voltages and errors of power supply currents. The algorithm is quite simple to implement, because it lacks difficult mathematical operations for calculating inverse trigonometric functions. The selection of the required output voltage vector of the SAPF inverter is determined by determining the location of the spatial vector of equivalent control in a stationary coordinate system α-β, the components of which are calculated in real time. The current tracking error sign using a quasi-stationary two-dimensional sliding surface and a circle-tolerant figure is estimated. The sliding surface is a linear combination of components of the two-dimensional current error vector of the RL filter. A simulation model was built and the simulation results are analyzed.

Grid connected inverters constitute the most important part of any modern day micro-grid. However, for the optimal usage of the resources, it becomes a necessity to track the dynamic changes in the plant parameters. In this paper, a parameter estimation architecture is employed in a synchronous frame of reference and the controller parameters are updated online. To verify the performance of the control come estimation architecture, a deadbeat control is implemented on a three phase grid connected inverter with RL filter. The controller parameter gains are adjusted based on the parameter estimated. Verification of the proposed methodology is carried out via simulation based on MATLAB/Simulink and PLECS domain along with experimental verification on a reduced scale laboratory prototype.

In this paper, a Ku-band tunable absorptive frequency selective reflector (TAFSR) is proposed. The TAFSR has a sandwich structure: an active resistive sheet at the top layer, and PEC at the bottom layer, divided by F4B substrate. The resistive sheet layer is composed of a simple straight strip between two metallic strips with PIN diodes loaded to get the tunable reflective coefficient. PIN diodes can be equivalent to serial RL circuit. Two metallic strips and the gap between units is equivalent to serial LC circuit to control the resonant center frequency. The biased strip can be equivalent to the parallel inductance circuit as the electric structure and the biased lines simultaneously. The influence of the PIN diodes' tunable resistance is analyzed through equivalent circuit model. The measurement results show that the −10dB tunable absorptive band of the proposed TAFSR can be achieved in Ku-band from 10.3 GHz to 19.2 GHz.

This work addresses the problem of negative incremental resistance behaviour that arises due to the impedance interactions between the power electronic converters that consists of an LC filter and a tightly regulated DC-DC buck converter. Failing to address this problem renders the cascaded system prone to instability. This paper introduces three different parallel virtual impedances, connected across the capacitor of the source side converter for restoring the stability and also for improving the dynamic performance of the load converter, during the external disturbances. The specific advantage of the proposed approach is that it requires the sensing of voltage across the LC filter rather than the current through the inductor in LC filter for designing the required virtual impedance. All these impedance configurations not only provide stability but also ensure a good dynamic response both across the LC filter and at the load converter's output voltage terminals. The response from the MATLAB/SIMULINK based simulations reveal the stability at steady state and the dynamic performance shows the improvement over a second order virtual impedance and an optimal method. Among the chosen impedance network configurations, the series RL network exhibits superior dynamic response to external disturbances. Analytical and simulation results of the work are included.

In this paper, the model and simulation in state space of a wind energy conversion system (WECS), using the type-4 wind turbine topology is presented. The model in state space of a wind turbine (WT) with direct-drive permanent magnet synchronous generator (PMSG) via full scale back-to-back converter integrated into the power grid using a RL filter is described. The particular interest in this work is to address the dynamic study of variable-speed wind, evaluating the performance of proposed control devices. The obtained results in the case study are validated against the obtained response with Matlab/Simulink®.

A combined control strategy of the three-phase shunt active power filter that is connected to a non-linear load network is proposed. The filter consists of a voltage source inverter on fully controlled switches, capacitor storage, and a first-order three-phase RL filter. The decomposition of the object of study according to the rates of motion of the dynamic system was performed. The fast subsystem is a circuit of compensation current control, the slow subsystem performs stabilization of the capacitor voltage. A double twisting algorithm to control the DC voltage is used. In it, to calculate the “operator variable”, in addition to the error of the capacitor storage voltage to increase the speed is also used its derivative. A two-dimensional sliding manifold to generate the compensating current is used. Each component of this surface is a linear combination of components of two-dimensional vectors. The first vector is the current error of the RL filter, the coordinates of the second are locally equivalent to the derivative of this error. The calculation of the instantaneous value of both components of the second vector by entering the second order sliding mode was forced. A simulation model is developed and the results of simulation are analyzed. A comparison of the proposed strategy with the traditional PI-regulation by the criteria of the duration of the transition process and the coefficient of harmonic distortions in the current consumed from the network is made.

This article provides two new features that in combinations facilitate the construction of a transfer function in RC and RL circuits, and in s-expanded polynomials. First is the introduction of tuple-based array manipulations, where multiplications and divisions are replaced with convolutions and deconvolutions, respectively. Second, it introduces a new UaL decomposition for tuple-based matrices. The UaL decomposition is proven to be computationally more efficient compared to the traditional LU factorization. It is shown that the growth of the entries in both U and L matrices are gradual and follow a geometrical pattern, as the decomposition progresses. Another important feature of the UaL decomposition is that it does not generate nonzero remainders, or simply, it is “cancellation free”. The method is applied to the MNA representation of an RC (or RL) circuit. Finally, it is shown that working in the tuple-based format puts the U and L matrix entries into s-expanded form, such as P(s) = a n sn + a n-1 sn-1 +…+ a 0 , which in turn produces s-expanded transfer functions.

A simple control strategy of the three-phase shunt active power filter that is connected to a non-linear load network is proposed. The filter consists of a voltage source inverter on fully controlled switches, capacitor storage, and a first-order three-phase RL filter. The decomposition of the object of study according to the rates of motion of the dynamic system was performed. The fast subsystem is a circuit of compensation current control, the slow subsystem performs stabilization of the capacitor voltage. An asymptotic double-twisting algorithm to control the DC voltage was used. For the current formation, a two-dimensional sliding surface is used, which is a linear combination of the components of two-dimensional vectors - the error of the current of the RL filter and some variable. The double-twisting algorithm to calculate the instantaneous value of this variable was also used. A simulation model is developed and the results of digital experiments are analyzed. A comparison of the proposed strategy with the traditional PI-regulation by the criteria of the duration of the transition process and the coefficient of harmonic distortions in the current consumed from the network is made.

This article presents a study of the photovoltaic grid connected system which has the ability to compensate the reactive power and to eliminate the harmonic currents. This system consists of two stages. The first is the boost converter which is controlled by the incremental conductance algorithm (INC) to extract the maximum power from the photovoltaic panels. The second stage is the inverter, which is controlled by a super twisting control to maintain the DC bus voltage at the desired value and to control the currents d-q of the RL filter. The system is simulated using MATLAB / SimPower System. The results show the high robustness of the super twisting control. Moreover, the current quality has improved where the total harmonic distortion (THD) has reduced.

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient., Accepted to the 57th Design Automation Conference (DAC 2020); 6 pages, 8 figures

In this paper, a decentralized control method is presented for the islanded inverter-interfaced microgrids with robust performance approach. The system is consisted of two Distributed Generations (DG) linked to their loads by inverter, RL filter and a step up transformer. The objective here is to guarantee the stability of the system and its desired performance under large load perturbation and Plug-and-Play (PnP) of the DGs. To achieve that aim, a Linear Matrix Inequality (LMI) state-feedback control technique with $H_{\infty}$ guaranteed cost is used for each DG. Contributions of the designed control system are: 1) the control design is entirely decentralized; 2) the stability and the desired performance of the overall system is guaranteed; 3) the control system is completely robust against PnP functionality of the DGs; 4) the controller provides robustness against large load perturbation. The ability of the presented control system with regard to voltage tracking, load changes and topology changes is evaluated on several case studies based on simulation in SimPowerSystems Toolbox in MATLAB.

This paper reports the designing of low noise amplifier (LNA) using the inductive source degeneration with cascode topology with different output matching stages namely resistive with inductive load (RL circuit) and inductive with capacitive load (LC circuit) in 45 nm CMOS process technology at 2.4GHz frequency. The implementation was done in Advanced Design System (ADS) software. The LNA obtained moderate gain of 5.046 dB, input reflection coefficient of -10.869 dB, maximum gain of 15.410 dB, and noise figure of 3.590 dB and with power consumption of 8mW for RL output matching network at 2.4GHz ISM band. For LC matching network, the LNA achieves high linearity 21.597 dB, high gain of 18.408 dB with low power consumption 2 mW, respectively.

In this paper we propose a Reinforcement Learning (RL) algorithm for path tracking of a real car-like robot. The RL network is trained in simulation and then evaluated on a small racing car without modification. We provide a big number of training data during off-line simulation using a random path generator to cover different curvatures and initial positions, headings and velocities of the vehicle for the RL agent. Comparing to similar RL based algorithms, we utilize Convolutional Neural Network (CNN) as image embedder for estimating useful information about current and future position of the vehicle relative to the path. Evaluations for running the trained agent on the real car show that the RL agent can control the car smoothly and reduce the velocity adaptively to follow a sample track. We also compared the proposed approach with a conventional lateral controller and results show smoother maneuvers and smaller cross-track errors for the proposed algorithm.

This work considers a modal vibration analysis of a thin aluminum square plate structure. The plate is submitted to harmonic excitation forces in a wide spectrum of frequencies to get its frequency response function and determine its resonance frequencies. The main objective is to model and experimentally validate the most significant resonance frequencies (MSRF) on the square plate, in order to analyze those that have more amplitude range and may cause damage to the mechanical structure. The application of finite element methods (FEM) and experimental modal analysis allows to compute the modal shapes associated with the specific resonance frequencies. Moreover, the existing damping on the plate structure can be modified by using an adaptive-like piezo-shunt vibration absorber. Such strategy can be implemented with a few piezoelectric patches and a particular kind of RL circuits, which can be tuned to minimize the vibration response of the plate structure at specific resonance frequencies.

This paper presents two CMOS designs of a second-order voltage-mode allpass filters (APFs) for high-frequency applications. Each of the proposed filters is based only on a single transistor and four surrounding impedances. The first proposed allpass filter is an RL filter while the second proposed one is an RLC filter. A detailed analysis along with the parasitic effects is provided for each of the proposed filters. As a proof of concept, one design was constructed and verified experimentally using discrete MOS transistors at a 2.3MHz pole frequency. The experimental results showed a group delay of approximately 165ns with a quality factor of 1. The second design was simulated in 65-nm CMOS process and demonstrated a group delay of 22ps within a bandwidth of 18GHz with total power consumption of 9mW.

Proposed work describes a new grounded lossy inductance (grounded parallel RL network) simulator configuration employing two Dual-output voltage-differencing buffered amplifiers (DO-VDBA) along with single capacitance. The presented circuit configuration is purely resistor-less active realization (Active-C realization) with electronic tuning of both inductive as well as resistive part through the transconductance of employed DO-VDBAs. The electronic tuning of inductive part is independent to the resistive part which is an important advantage. The presented realization is completely free from matching conditions and its non-ideal behaviour is satisfactory. To understand the high frequency performance of simulated lossy inductance its behaviour is studied considering terminal parasitcs of DO-VDBAs. The usefulness of developed circuit is authenticated by developing a second order voltage-mode high-pass filter design example. All the designed circuits are simulated in PSPICE environment.

Grid-connected inverters are conventionally controlled in synchronously rotating frame of reference with the controllers being designed for steady state operation via small signal modeling neglecting higher order and coupling terms. However, for an inverter connected to the grid via RL filter, cross coupling terms are present due to transformation to synchronously rotating dq reference frame, thereby affecting the dynamic performance. In this paper adaptive estimation based feedback linearization control is proposed for online parameter update to exactly cancel the non-linearity and higher order terms which reduces the system into bunch of pure integrators. The details of adaptive parameter estimation and the feedback linearization have been presented in this paper. Overall control architecture proposed in this paper is been verified via simulation studies based on MATLAB/Simulink and Plecs domain. A reduced scale laboratory prototype has been utilized to implement the proposed control architecture and verify its efficacy.

The aim of this work is modeling of a new topology shunt active power filter (SAPF) using instantaneous reactive power theory (IRPT) technique has been presented. The unipolar carrier based pulse width modulation (UCBPWM) technique using two different current control strategies (i.e. direct and indirect current control techniques) with PI controller has been used for generation of gate pulses for IGBT’s connected in voltage source inverter (VSI). The simulation model of three phase three wire power system with three phases shunt active power filter is constructed in MATLAB/SIMULINK and is tested for two different operating conditions (i.e. direct and indirect current control techniques). In this paper, shunt active power filter (SAPF) is constructed using DC storage capacitor and series combination of three phase VSI with three phase parallel RL filter. The parallel RL filter works as a high pass filter (HPF), in which inductor of RL filter works as a delta connected winding of three phase transformer. The simulation result indicates that, the indirect current control (ICC) strategy provides the better performance as compared to direct current control strategy. Since, the indirect current control (ICC) technique gives less harmonic compensation ratio (HCR) as compared to the direct current control (DCC) technique.

This paper describes wideband three-way Wilkinson power dividers using LC-ladder circuits. The proposed dividers consist of multi-section LC-ladder circuits between input and output ports, and their output ports are connected each other through external circuits composed of series RL circuits. By connecting the appropriate external circuits in accordance with the number of LC-ladder circuits, the proposed dividers can be realized extremely wideband operation. In order to verify the design procedure, wideband three-way Wilkinson power dividers are simulated and fabricated at VHF-band. As results of simulation and experiment, we can obtain broadband characteristics with a relative bandwidth of over 60%, which are near agreement with the theoretical results.

Currently, there is a significant increase in interest in distributed energy sources, in particular in CHP (Combined Heat and Power) systems. The article presents the interactions occurring in the co-generator between the combustion engine and the synchronous generator. The tests included adjustment of rotational speed and armature voltage. A zero-dimensional model was used to model the working cycle of an internal combustion engine, in which the release of chemical energy of a fuel is determined based on the Wiebe function. All thermodynamic processes were treated as non-adiabatic. To model the synchronous generator, the RL circuit model was used with one damping circuit in each axis.

Voltage Balance of the series-connected dc-link capacitors is the key problem of three-level diode-clamped converters. In this paper, an auxiliary voltage balance circuit (VBC) is presented to maintain the voltage balance of dc-link capacitors. The voltage balance circuit consists of a clamping capacitor and a current-limiting inductor. With the clamping capacitor, the voltage stresses of the auxiliary circuit devices are restricted to one half of the bus voltage, and the current ripple of the inductor is also effectively suppressed. The operating principles of the auxiliary circuit are studied, and a time-domain model is derived. Accordingly, a control algorithm of the auxiliary circuit is proposed based on finite-control-set model predictive control. Simulation results validate the effectiveness of the auxiliary voltage balance circuit. The auxiliary circuit is applicable for three-level DCI-based energy conversion systems, static reactive power compensations and medium-voltage highpower motor drives.

This paper presents a study about the impulse impedance of grounding grids based on experimental measurements performed within a testing field developed for this purpose. It considers an extensive number of measurement sets performed in grounding grids with different dimensions and topologies. The main goal is to evaluate an appropriate procedure to be employed during field measurements, as well as to verify the impulse impedance behavior in relation to low frequency ground resistance and ground grid topology. Field test results show a strong correlation among important quantities such as impulse factor, resistance and inductive reactance of an equivalent RL circuit, and the grids topology. These results may contribute to the development of a methodology, which aims to adequately estimate the impulse impedance of grounding grids as a function of the resistance measured at low frequencies and the grid topology.

This paper compares the design and performance of two controls for half-bridge converters with LCL output filters based on Virtual Circuit Design method, which is an intuitive way to achieve desired closed-loop behaviours as well as resonance damping and low-frequency behaviours. The first control is represented by a circuit employing a resistor in series with a converter-side inductor to stabilize the resonance while the second one by a resistor in parallel with a filter capacitor. This yields different low-frequency behaviours and different designs of the current controllers. Moreover, both circuits feature the adjustable virtual inductance to improve the bandwidth and the robustness. The experiment illustrates excellent performances from the step response and fair robustness against grid-inductance variation. ispartof: pages:1-10 ispartof: 2017 19th European Conference on Power Electronics and Applications, EPE 2017 ECCE Europe vol:2017-January pages:1-10 ispartof: European Conference on Power Electronics and Applications, EPE location:Warsaw, Poland date:11 Sep - 14 Sep 2017 status: published

For the study of switching transients in Extra High Voltage (EHV) networks it is common practice to model a relatively small part of the EHV network. The downstream network is either disregarded or modeled as a parallel RC or RL circuit, based on the powerflow, directly at the secondary side of the transmission transformer. In this paper an investigation for the extent and model type of the downstream network (below 380 kV) is performed. A detailed model for an example downstream network is developed. Different simplifications and equivalent models are compared in frequency domain and in time domain, during cable energization. The impact of the lower voltage network on both the maximum overvoltage and the harmonic content during energization is assessed. Moreover, components that are of major importance are identified and proper equivalent models for the downstream network are proposed. Simulation results show that in particular the type of the 150 kV network (underground cable or overhead line) affects greatly both the maximum overvoltage and the harmonic content during energization. On the other hand, the parameters of end customer loads have only minor effect.

This paper introduces a new DC solid-state circuit breaker (SSCB) concept using a small inductor, which is similar to the inductor used in electro-mechanical breakers. The new SSCB scheme uses the voltage inductor to activate a short circuit protection, in this way the circuit starts to open in the moment of fault condition to prevent the over load current.

This paper proposes a simple circuit configuration and a control strategy of Solid-State Transformer (SST). In the proposed circuit, it is possible to reduce the volume of heat sinks and passive components by using low voltage switching device with low loss characteristic and high frequency operation. Moreover, the circuit employed with the proposed control strategy operates stably even when the ripple voltage is large. Besides, the bidirectional operation of the proposed circuit is also confirmed by simulation. From the simulation result, the capacitance in each cell of the primary side (high voltage side) can be minimized to only 3 µF for 10-kVA system. Moreover, a miniature model with three cells is tested to confirm the fundamental operation of the proposed circuit. As a results, the sinusoidal waveform of the input current is obtained without the large distortion. the total harmonic distortion (THD) of the input current is 2.55%. In addition, it is confirmed that the primary side capacitor voltage of each cell is kept constant without the balance control.

Shifting medium-voltage networks to operate with the neutral grounded via a resistor or an RL circuit is the most promising approach to improving the reliability of electric power supply systems either with or without capacitive current compensating devices. The Smart Grid principles imply minimization of losses to consumers; therefore, the optimal solution for the neutral grounding mode can be reached only with automatically controlled grounding devices. The article is devoted to studying and elaborating algorithms and circuit arrangements for control of the resistor taking into consideration the entire set of conditions and requirements imposed on the characteristics of particular electric networks. The results obtained from simulation of transients triggered by ground faults for a range of initial conditions and network parameters are presented, and the optimal values of active currents, at which an arcing fault unconditionally transfers into a stable mode, are determined. Algorithms are suggested; and circuit arrangements of devices are developed to control the resistor installed in the neutral of compensated and non-compensated networks.

In this paper, we present a low power bump circuit for finding similarity between two voltages. The circuit is based on a voltage correlator that in combination with a differential pair achieves the low power behavior. The circuit has low power consumption and low sensitivity when the different between the two input is large, but as they approach each other the sensitivity increases. The proposed circuit is very simple in design and can have more than 4 orders of magnitude less power consumption than the normal bump circuit.

This paper proposes a quantitative design method for a linear AC LED driver with a multi-level structure and a variable current regulator. The currently proposed circuit with a variable current regulator was found to drastically reduce the number of required circuit components by realizing a sinusoidal input current with only a single row of LEDs. However, it is necessary to adjust the parameters of the circuit components through simulations to properly design the circuit and realize its stable operation. In this paper, the operation of the currently proposed circuit is first described. Second, the losses of the circuit are calculated. The quantitative design of the circuit parameters is then suggested. Third, an experimental efficiency of 92.3% was confirmed, and the calculated and simulated efficiencies were 93.1% and 93.4% under the same design conditions. The experimental efficiency of 92.3% is 5.6% higher than that of the previous design. Next, a thermally designed circuit board was designed using a simulation for practical installation. Finally, conduction noise was experimentally measured.

This paper presents Series-Parallel Topology (SP) of magnetic coupling system for use in Wireless Power Transfer (WPT) applications. Configuration of the system is composed of rectifier circuit, inverter circuit and resonance circuit. Full bridge inverter circuit is powered by rectifier and its output is connected to the LC series resonant circuit. Moreover, the LC parallel circuit with resistance is serve as load of the topology. Electric equivalent circuit model is use to describe PS which yields reflected voltage, primary and secondary current and impedance of the system. The theory of the system is verified using an experimental setup connected to a circular primary coil and secondary coil. Various experiments are conducted for difference distance, arrangement, frequency, angle, and diameter. The analysis compares the efficiency of SP topology and its results are reported.

Stability analysis and measurements are presented for negative capacitance and negative inductance designs of digital non-Foster circuits that include a series resistance and model the effects of latency. Such digital non-Foster circuits provide a new important alternative to analog non-Foster circuits, with potential to address stability and performance issues in important non-Foster application areas such as metamaterials, acoustic cloaking, and electrically-small antennas. The proposed approach includes a resistive component in the signal processing of digital non-Foster RC and RL circuits to help control stability and to mitigate parasitic resistance, and also includes latency effects associated with computation and conversion time. Analysis, simulation, and measured results confirm the desired non-Foster impedances, and show useful regions of stability as a function of resistance and latency.

A new technique is presented to convert an RC or RL circuit to its corresponding LC circuit. It is shown that while this conversion keeps the coefficients of a transfer function unaltered, it maps the roots (poles and zeros) of the transfer function to desirable locations for further processing. The technique provides different results for different types of (real, imaginary, and complex) roots on the s-plain, which in fact lends itself to identifying and even extract the circuit roots directly from a Bode plot. Some applications of the methodology with examples are given to demonstrate the capability of the technique.

Approximate analytical solution of linear or nonlinear ordinary differential equations (ODE) can be obtained by Adomian decomposition (ADM) method. The nonlinearities in the ODEs are approximated by Adomian polynomials and a rapidly convergent sequence of approximate functions will be obtained as a solution. The ADM is widely used for numerical simulations of real-world systems in the applied sciences and engineering including nonlinear ODE and DAE problems. Multi-stage Adomian decomposition method (MADM) extends the region of convergence of ADM by integrating over multiple overlapping time intervals. In this paper applicability of the MADM for real-time simulation has been investigated for the first time. 3-term approximation of MADM is used for the solution of a series RL circuit, buck converter and boost converter. Mini-FSS, an indigenous real-time simulator developed under National Mission on Power Electronics Technology (NaMPET) Phase II, government of India, has been used in this paper. The results of the MADM simulation are compared with the Backward Euler method on mini-FSS. The MADM accuracy and the execution times are found to be comparable to the Backward Euler method.

The Cauer-equivalent circuit of electric apparatus is synthesized by applying the model order reduction to the finite-element equations. In this method, the admittance function of a given electric apparatus is expressed by a rational polynomial from which the Cauer-equivalent circuit is directly synthesized. Magnetic saturation in the magnetic core is considered by introducing nonlinearity in the primal inductance of the circuit. The synthesized circuit is shown to express the input-output properties of inductors and induction heating devices in good accuracy.

This paper describes the design of a high efficiency energy harvesting circuit combined with antenna. The circuit is composed of a series resonance circuit and boosting rectifier circuit for converting radio frequency power into a DC boosted voltage. For further efficiency improvement, input impedance of antenna is optimized. The simulated output DC voltage is 9.0V for an input of 100mV at 900MHz.

This study proposes a voltage equilibration circuit with a self-oscillation circuit for application to electric double layer capacitors (EDLCs). In typical monitoring circuits, multiple EDLCs are connected in series and the circuits are connected to a power supply. In contrast, the proposed circuits uses a self-oscillation technique, and its voltage is supplied by the EDLC, greatly simplifying the circuit structure. In particular, the circuit comprises only 15 electrical components and self-oscillates without a dead-time control circuit. Moreover, the circuit prevents the flow of the short-circuit current into the drains of the FETs. which causes overcurrent circuit damage. Further, the circuit can be constructed into a module of two serially connected EDLCs. The characteristics and usability of the proposed circuit are evaluated in a simulation and experiment.

In this article a new technique of process variation estimation in electrical circuit is presented. Technique is based on interval analysis application for a ladder circuit. Using this particular class of electrical circuit high speed of calculation could be achieved which is important in optimization and automated synthesis. In the article general ability of the technique application for a resistor circuit (with real impedance) is shown. Also ways of the technique extension for general circuit (with complex impedance) is discussed. Now the technique application is limited to passive network. The numerical experiments showed an agreement obtained results with statistical modeling with Monte Carlo Method. Further development of the technique is the extension to microwave circuit.

In this paper, a generalized fractional-order form of the simulated inductor using a single current feedback operational amplifier (CFOA) and a fractional-order capacitor is introduced. Analytical expression of the equivalent fractional-order inductor versus the circuit elements is achieved. Moreover, the effect of the parasitic impedance and the non-idealities of the CFOA are investigated analytically with numerical simulations and circuit equivalent. Circuit simulations are discussed using AD844 spice model to validate the theoretical study of the fractional-order inductor. Simulations show an extra degree of freedom in selecting the impedance value and the phase shift compared to the conventional realization. As an application, a fractional order low pass filter is simulated to verify the performance of the proposed circuit.

This paper presents a virtual circuit controller (VCC), which provides a systematic structured method to stabilize the resonance of an LCL filter in a grid-connected voltage source converter. The semiconductor switches are controlled to mimic the behaviour of a virtual reference circuit. The properly-damped circuit by a resistor in parallel with a filter capacitor is focused on and selected as the reference circuit. A linear transformation matrix is introduced indicating the resemblance between the physical and virtual circuits, and is employed to map the states between both circuits. Accordingly both analog and digital control laws are systematically computed. The insight into the feedback of the capacitor current and voltage through proportional gains is clarified. While the consequence of the former is conventionally known to emulate a resistor for damping purpose, the latter is newly used to emulate an inductor for adjusting the inner-loop control bandwidth and improving the robustness. A Kalman filter is used to deal with the inherent time delay. The detailed discrete-time state-space model of the complete system is derived. The design example of the proportional current controller is demonstrated. The simulation results illustrate the effectiveness of the damping and the robustness of the system against component-value variations.

This paper presents a process, voltage, and temperature (PVT)-independent constant-gm bias circuit, designed in 0.18µm CMOS technology. In this paper, the conventional precise off-chip resistor is replaced by a MOSFET operating in triode region with a novel bias circuit, which behaves like a PVT-independent resistor. Simulations show that the maximum gm variation across process corners is ±5.2%, and the worst temperature coefficient across temperature range of −40°C to 85°C is ±570ppm/°C. The variation of gm is 1.1%/V across supply voltage range of 1.5V to 2.5V at 27°C. The whole circuit consumes 83µW with supply voltage of 1.8V.

Multi-cell diode-capacitor/inductor based boost derived DC-DC converter provides a simple solution for high step-up voltage regulation in solar and fuel cell generation. However, many passive components increase the order of system model and complexity. Transient modeling analysis reveals that time constant of each component in diode-capacitor/inductor network is much smaller than that of other circuit if the directly charging and discharge processes between capacitor through diode is fast enough. The voltage/current relationship of each capacitor/inductor in multi-cell network is fixed. Multi-cell diode-capacitor/inductor network can be seemed as multi-stage DC transformer. Based on the unique feature, this paper proposes the reduced-order modeling approach for high step-up DC-DC converter with multi-cell diode-capacitor/inductor network. Finally, simulation and experiments verify the correctness and effectiveness of new modeling approach. The unified reduced-order model contributes to better understanding of circuit characteristic and simplification of controller parameters design.

One important issue related to the standard CMOS technology is a low-resistivity silicon substrate that results in low Q-factor for the passive spiral inductor. Therefore, active inductors have widely studied and applied to different range of RF circuit applications due to high-Q, low insertion loss, small size, and inductance tenability [1]. However, the conventional active inductors have also some drawbacks such as high noise figure, poor linearity, and high power consumption [2]. Moreover, most of the previously studied active inductors were basically grounded-type 1-port network. In this paper, a design of novel active 2-port inductor using LC parallel resonator is presented. The parasitic capacitances are decreased by adding parallel L f and C f to gates of M 1 and M 2 , as a result the Q-factor of overall circuit can be improved. The simulation was performed in Cadence Spectre by using SP simulation. The overall circuit size of the proposed active inductor is 0.45mm × 0.5mm including the pads, where the active area occupies only 0.2mm × 0.15 mm. The proposed circuit consumped 3.6mW DC power at 1.8V supply voltage. On wafer probing was used to characterize 2-port S-parameters of the proposed circuit and also a pad de-embedding method was used for accurate measurements. Figs. 1 and 2 show the simulated and measured inductances and Q-factors of the fabricated circuit. From an experiment, it is found that the inductance and Q-factor are higher than 2 nH and 50, respectively, in the frequency range of 1–6 GHz. The simulated and measured noise figure of the fabricated circuit is shown in Fig. 3. The measured noise figure is less then 12 dB in constant inductance range. The proposed circuit provides high inductance, Q-factor, low DC power consumption, and low noise figure over wide frequency range. The proposed 2-port active inductor is applicable in various RF circuits and systems such as coupler, RFIC filters, power dividers, and LC-VCO.

Previous design approaches for digital discrete-time non-Foster circuits have typically employed ideal current-output digital-to-analog converters to establish port currents based on measured voltages. In this paper, the design of digital discrete-time non-Foster circuits is presented for the case of voltage-output digital-to-analog converters with finite source impedance. These finite-impedance converters act as Thevenin sources that can be converted to Norton-equivalent sources for design and analysis. However, it is also straightforward to incorporate the finite source impedance directly into the signal processing, and this is the approach presented. In addition, it is often desirable to add series resistance to improve stability or to mitigate parasitic resistance, so the design of series resistor-capacitor and series resistor-inductor digital discrete-time non-Foster circuits are considered. Finally, unavoidable time-delay latencies associated with conversion time and computation time are also included.