Search

The detector at CERN's large hadron collider (LHC) was exposed to proton-proton collisions from beams crossing at 40 MHz. A three-level trigger system will select potentially interesting events in order to reduce this rate to 100- 200 Hz. A trigger decision is made by the Level-1 central trigger processor (CTP) reducing the incoming rate to less than 100 kHz. The Level-1 decision is based on calorimeter information and hits in dedicated muon trigger detectors. The final Level-1 trigger system is currently being installed in the experiment with completion expected in autumn 2007. Cosmic ray data are regularly recorded as an increasing fraction of the trigger system comes online. We present an overview of the Level-1 trigger system architecture and report on the installation and commissioning process at the ATLAS experimental site. Emphasis is put on the integration of the CTP with the calorimeter and muon trigger systems. We show results from analyses of cosmic ray data recorded in situ and verify, where possible, that the Level-1 trigger meets the requirements and will be ready for data taking.

A prototype first-level calorimeter trigger for use at LHC is described. The trigger is designed to operate on analogue signals sampled every 15 ns, the original design period for LHC. The prototype system takes in signals from a 6x6 array of calorimeter cells. These are digitised by FADCs and are then sent to a cluster finding module which contains nine ASICs based on a 0.8 micron CMOS gate array. Each ASIC searches for isolated energy clusters within the array and also calculates the sum of the energy in all 16 cells. The energy threshold of the cluster and of the isolation window are field programmable. The performance of the trigger has been evaluated both with test systems and in real conditions connected to a liquid-argon electromagnetic calorimeter in a test beam at CERN. The latency of this pipelined trigger system is 175 ns, including digitisation and digital processing.

The level-1 calorimeter trigger consists of a preprocessor (PP), a cluster processor (CP), and a jet/energy-sum processor (JEP). The CP and JEP receive digitised trigger-tower data from the preprocessor and produce regions-of-interest (RoIs) and trigger multiplicities. The latter are sent in real time to the central trigger processor (CTP) where the level-1 decision is made. On receipt of a level-1 accept, readout driver modules (RODs) provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the level-2 trigger. The level-1 calorimeter trigger system at the test beam consisted of 1 preprocessor module, 1 cluster processor module, 1 jet/energy module and 2 common merger modules. Calorimeter energies were successfully handled throughout the chain and trigger objects sent to the CTP. Level-1 accepts were successfully produced and used to drive the readout path. Online diagnostics were made using 4 RODs. Energy histograms were plotted and the integrity of data between the different modules was checked. All ATLAS detectors in the test beam were able to build full events based on triggers delivered by the calorimeter trigger system.

The proposed level-1 calorimeter trigger system for ATLAS relies upon several key technologies which we have been testing in a demonstrator programme. We describe here the final phase of this programme, which concentrates on crucial aspects of high-speed data transmission inherent in the trigger architecture while operating with signals from prototype ATLAS calorimeters. The 36-channel trigger demonstrator system has been designed to provide a flexible infrastructure for the study of alternative techniques of communication between the calorimeters and the trigger processor, including both analogue links and high-speed digital optical and electrical links operating at up to 1.6 Gbaud. Data fan-out at 160 Mbit/s between trigger processor modules using serialising Application Specific Integrated Circuits (ASICs) driving transmission-line backplanes is also evaluated. A programmable timing system re-synchronises all channels before pipeline processing by ASICs executing an electromagnetic cluster-finding algorithm. Some preliminary results are presented from the operation of this demonstrator system installed in the ATLAS test-beam at CERN.

Attention is given to the High-Performance Parallel Interface (HIPPI), a new ANSI standard, using a minimal protocol and providing 100-Mbyte/s transfers over distances up to 25 m. Equipment using this standard is offered by a growing number of computer manufacturers. A commercially available HIPPI chipset allows low-cost implementations. A brief technical introduction to the HIPPI is given, followed by examples of planned applications in high-energy physics experiments, including the developments involving CERN: a detector emulator, a RISC, (reduced instruction set computer) processor based VMEconnection, a long-distance fiber-optics connection, and a HIPPI testbox. >