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A current-mode photon-counting circuit is proposed for long-range LiDAR applications to interface with a microchannel plate (MCP) photomultiplier tube (PMT). Based on the idea of a current-mode comparator, the proposed topology combines a BiCMOS regulated cascode current buffer together with a CMOS current comparator. The circuit accepts two input current signals, the photodetector current and a user-adjustable threshold current, and outputs a 1.8-V digital signal depending on the polarity of the difference current. Designed and characterized in a 180-nm SiGe BiCMOS process, the proposed design provides a 50-Ω input impedance up to 2-GHz and can detect 8-uA current pulses with widths of 300-ps FWHM at a count rate of 1-GHz. The solution also offers a low static power consumption of 4.07mW/channel dissipated from a 2.5-V and 1.8-V dual supply.

A chopping technique in a continuous time K-delta-1-sigma modulator (KD1S) is reported in this paper. It is shown that the presence of the inherent path filter in the proposed technique can significantly improve the performance of the modulator by minimizing the aliased quantization noise. Also reported are how the selection of chopping frequency and its relation to sampling frequency and the trade-offs. To support the theory, a first order K-delta-1-sigma topology was designed in a 180nm CMOS process. Simulations are used to illustrate the validity of the results. The modulator works at a sampling frequency of 1 MHz with an oversampling ratio of 256. It consumes an average current of 61.18 µA from 1.8 V supply. The simulation result shows that there is more than 25dB improvement in the Signal-to-Noise Ratio (SNR) of the KD1S, when chopped at the right frequency.

Photon counting techniques are becoming more critical in fields such as LiDAR, high energy physics (HEP) and positron emission tomography (PET). For space-based aerosol-cloud-ocean (ACO) LIDAR, the total aggregate photon flux signal has a very high dynamic range from a single-photon up to giga-photons per second for a single channel. A current-mode front-end can accommodate this counting dynamic range over a wide range of input signal current pulse amplitudes. A multi-channel current-mode photon counting circuit was designed, simulated, and fabricated in a standard 180 nm SiGe BiCMOS process. This photon counting circuit achieved a maximum count rate of 500 MHz with a 300 ps FWHM pulse width at amplitudes of 5μA to 1.25 mA.

A low cost, low power substitute for expensive, high power high-speed analog-to-digital converters (ADCs) in some situations is presented. This circuit is called a variable fast transient digitizer (VFTD). This paper provides an overview of the design and measured test results. The VFTD is designed to sample a high-speed analog input signal and later reconstruct the captured signal at a much slower rate, for example, around three orders of magnitude. This approach eliminates quantization error in the captured signal. Further, this approach enables the use of slow, low cost, analog-to-digital converters such as those found in microcontrollers. The VFTD discussed in this paper uses 256 sequential sample and hold cells with a process dependent variable delay element controlled by an off-chip voltage source. Using a power supply voltage of 5V the input range extends from 0 V to 3 V corresponding to an output voltage range from 2 V to 5 V, a capture window range from 81 ns to 1.78 µs, and a sampling rate range from 143.82 MS/s to 3.16 GS/s. The VFTD is fabricated on a 2 mm x 2 mm die using ON Semiconductor's 0.5 µm C5 process and requires a 0.5 mm x 1.5 mm area.

A digital silicon photomultiplier (SiPM) using segmentation technique is designed, simulated and fabricated in the AMS 0.35 µm SiGe BiCMOS process. The digital SiPM is intended for photon counting applications. The digital SiPM consists of 16 avalanche photodiodes (APD) each with active area of 24 µm x 24 µm arranged in a 4x4 array with series 236 kΩ quench resistors. The SiPM has a peak responsivity at 490 nm wavelength and a fill factor of 12.6 %. The digital SiPM generates an output 5-bit digital word that indicates the number of APDs triggered in the SiPM array at the rising edge of clock. Simulation results show that the digital SiPM can work at a maximum speed of 100 MS/s and uses 64.6 mW of power. The digital SiPM occupies an area of 0.38 mm2.

An externally triggered analog sampling circuit used as an alternative to a high speed analog-to-digital converter (ADC) in microcontroller systems is designed, fabricated and characterized. High speed ADCs are expensive in terms of cost and power dissipation, the fast transient digitizer (FTD) is a low cost alternative and has no appreciable DC power dissipation. The transient digitizer uses cells with a process dependent delay element to sample data onto hold capacitors. The hold capacitor drives a PMOS source follower that is activated by an NMOS switch. The switch is controlled by on-chip logic that reads each sample sequentially in conjunction with an external counter. The FTD can capture an input signal with a maximum duration of 25 ns and an input range of 0 V to 2 V. The output is a reconstruction of the input signal on a timescale up to a few hundred μs. Two FTD circuits are fabricated on a 1.5 mm × 1.5 mm die using a 500 nm CMOS process; one FTD circuit occupies an area of 1.057 mm × 0.461 mm on the die.

This paper describes a feedback time difference amplifier (FTDA) with good linearity and high gain for coarse-fine time-to-digital converters. The symmetrical FTDA has two identical output generators. Each one consists of one SR-latch, one XOR gate, one buffer and two feedback P-type keepers. The improvement in linearity and time difference gain is achieved with two feedback paths based on meta-stability of the SR-latch. Its validity was demonstrated using 130nm CMOS technology. The power consumption is 91.54uW for the highest gain at 2MHz input signals. The gain can be controlled from 25.06 to 734.9 with a ±20ps input time interval.

A grid-tied photovoltaic (GTPV) in conjunction with the proper energy storage system, have the potential to increase electrical power quality and reliability. This paper highlights the key dynamics behind GTPV energy storage sizing. Brief assessments on the merits of energy buffers for solar GTPV are presented. Also presented is an economical framework that may help policy makers assess all the benefits in order to manage the trade-offs intrinsic to renewable technologies. Study results showed that 245Ah and 2.5 kAh buffers were needed to produce 6 kWh per day for 30 minutes and 60 kWh per day for 5 hours, respectively. Results also revealed that the “customer-generator” GTPV system has cut the electricity bills significantly down, 36.45 percent, throughout the study year.

Transient heat transfer analysis by means of analytical methods is known to be cumbersome. This paper seeks to develop an LTspice model of a real-world solar thermoelectric generation system. The thermal parameters of the proposed model were extracted from a multitude of parts' geometries and properties. These parameters were then converted into their electrical equivalences through the “thermal-to-electrical analogy.” In addition, real site data were fed into the Spice model via the built-in piecewise linear command in order to implement the real system's thermal behavior. An interesting RC analogy was derived from this model in order to demonstrate how thermoelectric generation systems respond to square wave-like solar radiation. Although temperature variations on the cold side of this LTspice model are roughly 80% accurate, simulation results and the actual experiment remain in good agreement.

A computer vision assisted displacement measurement technique is proposed in this study. A sharp micro-marker is used as the marker of the bimorph piezoelectric actuator (PZT-5H). The micrometer actuation of the PZT-5H is monitored by a high resolution stereomicroscope. The micro-marker actuation is recorded as the driving voltage increases. Post image processing of the captures are conducted by MATLAB. The extracted vertex pixel values of the micro-marker from the captures are used to represent the PZT-5H actuation. The driving voltages are varied from 0 to 190 V which induce maximum displacements of 300 μm (1029 pixels). The proposed system can resolve a minimum displacement of 248 nm (1 pixel). Voltage to displacement linearity and repeatability are investigated. The PZT-5H chip has good linearity with driving voltages between 10 and 90 V. Future applications of this measurement technique are discussed.

A passive 2nd-order sigma-delta modulator using switched-capacitor based filters was designed, fabricated, and tested. A novel 2nd-order single feedback path topology is used. All circuitry is optimized for low power operation through the use of minimum size MOSFETs, component reduction and topology choice. The modulator was fabricated in On Semiconductor's C5 500-nm process. The implementation achieves a typical SNDR of above 50 dB for tested frequencies of 10 Hz to 3 kHz and has a peak SNDR of 57.8 dB, which corresponds to an ENOB of 9.3 bits. With a 2.5 V supply, the power consumption of the sigma-delta modulator is 6.75 μW. The modulator achieves a FOM of 1.78 pJ/step.

A highly efficient and reliable electrowetting on dielectric (EWOD) digital microfluidics (DMF) chip is proposed. An 8 μm parylene C layer is used as the dielectric material. Extra vapor-phase silane (VPS) is introduced into the chamber and acts as an aerosol primer to enhance the chemical adhesion to the parylene C surface. The EWOD chip can perform droplet dispensing, merging and splitting smoothly in an air ambient. Dual electrode dispensing mode (DEDM) and single electrode dispensing mode (SEDM) are tested to investigate the dispensing volume accuracy. Small deviations (0.0467 μL for DEDM and 0.0303 μL for SEDM) are observed for the dispensing. Droplets from 1.5 μL to 2.3 μL are tested for the minimum splitting voltage. Larger droplets require larger voltages to be split. The proposed EWOD chip is promising for future point-of-care clinical diagnostics.

The displacement of an intelligent PZT (piezoelectric materials based on modified lead zirconate titanate) controlled EWOD (electrowetting on dielectric) top plate is modeled by inverse Preisach hysteresis algorithm. First, the PZT deflection model is created from an experimental displacement dataset. The real time output is predicted based on the previously stored weighting functions. Upon the desired output and the current input, the input voltage is compensated by a feedforward voltage which is derived from the model using a closest match method. The feedforward process and the model are stored in a PC. A portable high voltage DAC (digital-to-analog converter) is used to drive the PZT cantilever structure. The worst-case DNL of the high voltage DAC is 0.8125 mV. The tracking errors of a 0.067 Hz triangle wave input are less than 5 μm. Results show the inverse Preisach model is a good candidate for precise EWOD top plate displacement hysteresis compensation.

This paper presents a comprehensive method of extracting thermal to electrical parameters that appear in a thermoelectric module (TEM). A step-by-step procedure was developed and followed to succinctly extract the parameters needed to model the TEM. These parameters include the Seebeck coefficient, electrical conductivity, thermal resistance, and thermal conductivity from a datasheet. Data extracted from the manufacturer datasheet, material properties, and geometries were successfully utilized to compute the thermal capacities and resistances necessary to perform the thermal to electrical conversion steps required for simulation accuracy. In addition, temperature variations of the intrinsic internal parameters were accounted for in this process. The aforementioned extracted parameters are compatible with the LTspice circuit simulator and other related software. The steps that it takes to simulate any thermo-electrical system with the LTspice simulator are not only found to be of two kinds, but are also thoroughly explained in this paper.

An improved SPICE model for a thermoelectric generator (TEG) is presented. Temperature variations of the intrinsic internal parameters are included in the proposed model. For accuracy in the proposed model, the internal parasitic components effects and the temperature dependence of the parameters that occur in any thermoelectric module (TEM) were taken into account. Experimental results were compiled in the form of a lookup table and then fed into the SPICE simulator using a piecewise linear (PWL) model in order to validate the model. Experimental results showed that a differential temperature of 13.43°C was achievable whereas the SPICE model indicated a temperature gap of 9.86°C with the higher error being associated with the hot side. Overall, both experimental and simulated results were in a good agreement.

Methods to mitigate the effects of power transients associated with grid-tied concentrated photovoltaic systems due to fast-moving cloud coverage were assessed. The approach was to buffer intermittency of concentrated photovoltaic output power with used electric vehicle batteries. The main goals of using grid-tied photovoltaic in conjunction with the proper energy storage (340kWh) were 1) to smooth out the intermittent solar power and 2) to defer part of the peak load to a convenient time with a proper control strategy. Real data from the summer of 2011 were utilized to conduct this study. Hence, simulation results showed that not only the unit was capable of putting a constant amount of power (20 kW) onto the grid, but also was able to shift the less valuable off-peak electricity to the on-peak time, when the price of electricity cheaper.

Energy storage systems are one of the major components in today's grid-tied photovoltaic technology. The most widespread ESSs are the batteries mounted on electric vehicles. Second-life batteries, regardless of the technology, are less expensive than new battery packs. The proper sizing of concentrated photovoltaic buffers and the true economic feasibility need to be investigated thoroughly before any large-scale photovoltaic grid integration. This paper investigates the economic performance of grid-tied concentrated photovoltaics and buffers. Simulation results show that not only is the combined unit capable of connection to the grid during the day at a constant 20 kW, but also was able to shift the less valuable off-peak electric supply to the on-peak supply, where the cost of electricity was higher. This paper addresses 1) techniques behind battery-sizing scenarios, 2) battery-parameter calculations involved in concentrated photovoltaic output smoothing and/or electrical load shifting, and 3) used electric vehicle battery cost estimation. Estimates of the cost effectiveness could be positive if the energy storage system battery pack prices drop to $375/kWh or lower.

An FPGA based 2nd-order passive KD1S sigma-delta modulator was designed, simulated and tested. The design is implemented on an Altera Cyclone IV EP4CE115 FPGA. All active components such as digital logic, clock circuitry, and registers are located internally on the FPGA chip with only passive RC lumped analog components located off chip. The circuit uses eight logic elements and two PLL blocks on the FPGA to create an eight path KD1S sigma-delta modulator. The design performance was quantified at effective sampling rates of 80 MHz and 450 MHz. The implementation achieved a peak SNR of 58 dB and an ENOB of 9.3 bits at a 450 MHz effective sampling rate. The key benefit of this approach is the absence of active analog components, very low power, and high-speed sampling.

An ultra-sensitive electrowetting on dielectric (EWOD) capacitance measurement system is proposed in this study. A 24-bit integrated circuit (IC) capacitance-to-digital (CDC) sensor is used to convert the capacitance changes caused by variations in droplet volume and concentration to digital data. A 2.3 mm by 2.3 mm printed circuit board (PCB) based electrode pair is used to sense the analog capacitance change. The capacitance of pure water and NaCl solutions are tested by the CDC system. Desktop-drawing software is used to fix the position of the droplet to obtain a small capacitance deviation of 10 IF. Result shows the CDC system can resolve the capacitance changes caused by adding 0.1 micro-liter droplets or by increasing the NaCl concentration by 1%. The digital output of the sensor is interface-friendly to microcontrollers.

A passive 2nd-order sigma-delta modulator based on a cascade of first-order lowpass filters was designed, fabricated, and tested. A lumped RC filter is added in the loop of a conventional 1st-order passive sigma-delta modulator in order to improve the linearity of its transfer function. A low power edge-triggered comparator was designed and fabricated along with lumped components in ON Semiconductor’s C5 500-nm process. The implementation achieved a THD below 1% for all frequencies between 10 Hz and 5 kHz. With a 5 V supply the power consumption of the sigma-delta modulator is 64.5 uW to 150 uW depending on the input signal.

Droplet actuation, merging, and splitting using controlled electro-wetting are implemented on the top of a standard printed circuit board (PCB) resulting in a fast prototyping microfluidic platform for biological experiments. In the system reported here the PCB is used as a substrate and is covered with Saran Wrap. The Saran Wrap can then be coated, or not, with a commercial water repellent liquid. The resulting hydrophobic surface is used as a supporting dielectric layer for the experiments. Results show that lower actuation voltages and frequencies are achieved, than previously reported, to move larger droplets (30 microliter). Single-plate and dual-plate techniques are compared showing that a single-plate system can utilize lower voltages while at the same time being simpler to construct. The platform is designed for tissue immunohistochemistry staining experiments. Keywordselectro-wetting; immunohistochemistry; low voltage; printed circuit board (PCB) microfluidics

Avalanche photodetectors (APDs) have been fabricated in ON Semiconductor's C5 process without any special process or fabrication steps. The electrical and optical characteristics of APDs, with varying active area and guard ring configurations, are reported in this paper. Also reported are the details and considerations that went into laying out the APDs. It was found that substrate current was negligible and nearly independent of the geometrical shape of the substrate tie-downs around the perimeter of the APD structures. The measured APD breakdown is approximately 14 V. The devices show optical gains in excess of 1,000 at photocurrents of 10 µA.

A per-column, delta-sigma, analog-to-digital converter for use in CMOS image sensors is reported. Two techniques, subtraction and preconditioning, are proposed to compensate for the column-to-column mismatches and the resulting fixed-pattern noise introduced into the image. Equations governing the operation of the proposed topology are developed. Experimental results verify that even in the presence of very large offsets, such as a 200 mV mismatch in the MOSFETs' threshold voltages, the proposed topology operates as desired.

As CMOS technology scales to nanometer dimensions, analog-to-digital converter (ADC) design has become increasingly more challenging. This is mainly due to the increased transistor leakage currents, process variations, and poor matching. The K-Delta-1-Sigma (KD1S) modulator was proposed as a practical solution for designing high-speed ADCs in nanometer CMOS processes. This paper presents an 8-path KD1S modulator with an effective sampling frequency of 2 GHz derived from a 250 MHz input clock. The simulation results confirm the true first-order noise shaping of the modulator. The simulated SNR is 44.95 dB and the simulated SNDR is 44.41 dB corresponding to N eff = 7.17 bits with a conversion bandwidth of 15.625 MHz.

A 4 Gb DRAM architecture utilizing a scalable number of data pins is proposed. The architecture does not impact chip size and does not require additional metal layers. The 4 Gb DRAM measure 68.88 mm2 and achieves an array efficiency of 59.9%. This was accomplished by using a split bank, edge I/O interface, central row, and central column structures. The architecture coincides with the chip size and array efficiency measurements predicted by the ITRS for a 40 nm 2012 production DRAM architecture.

Over the past decade CMOS technology has been continuously scaling which has resulted in sustained improvement in transistor speeds. However, the transistor threshold voltages do not decrease at the same rate as the supply voltage (V DD ). Besides, the open-loop gain available from the transistors is diminishing. This trend renders the traditional techniques, like cascoding and gain boosting, less useful for achieving high DC gain in nano-scale CMOS processes. Thus, horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low-V DD processes. This paper presents a design procedure for op-amp design using split-length compensation. A reversed-nested split-length compensated (RSLC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RSLC topology is then extended to the design of three-stage fully-differential op-amps.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fully-differential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 µm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.

The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proximity communication promises to increase the off/on chip bandwidth of DRAM products while reducing the power consumption of the main memory system. The design of a memory system employing 4 Gb DRAM chips with a 64- bit wide communication bus using proximity communication is proposed. Technological roadblocks are analyzed and novel solutions are proposed. The proposed 4 Gb DRAM architecture can reduce the power consumption of a main memory system by 50% while increasing the bandwidth by 100%. The 4 Gb chip architecture measures 68.88 mm2 and has an array efficiency of 59.9%. The estimates are comparable to 2012 International Technology Roadmap for Semiconductors' (ITRS) estimates of 74 mm2 and 56%, respectively.

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. This includes lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADC is required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset error in its transfer function, which will lead to fix pattern noise. Correcting these gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. Therefore, a technique to minimize the effects of gain error in a delta-sigma modulation ADC for CMOS image sensor is discussed.

A monolithic integrated chip-scale surface plasmon resonance (SPR) sensor is demonstrated. The device consists of a pn photodiode covered with a periodic modified thin metal film whose lattice constant is on the order of the wavelength of light. The device performs real-time measurement of resonant wave-lengths of enhanced optical transmission due to surface plasmon resonance, which are influenced by the presence of chemical or biological materials at the device's surface.

As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes the K-Delta-1- Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared opamp and K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area.

We have demonstrated that back-end-of-line (BEOL) processing can successfully be performed in a university environment on die that have been fabricated at a foundry. This processing option enables universities to integrate state-of-the-art feature sizes with low resolution photolithography capabilities, such as achieved with a contact aligner, typically available at universities. With this capability, new device technologies and materials can be explored at the university level, where the basic research on the technology can occur without the timelines and expectations that are placed on product development in an industrial setting. By incorporating state-of-the-art feature sizes with these research efforts, the research results will be more applicable and more easily transferable to an industrial environment. In our project, we have demonstrated the integration of a foundry processed chip with the BEOL university processing through the fabrication of a small phase-change memory array with CMOS access transistors and addressing circuitry wherein the phase-change memory material was processed BEOL at Boise State University.

This paper presents the design and experimental results of W-2W current mirror binary-weighted current steering digital-to-analog converter (DAC) and its application for programming phase change memory (PCM). This new approach significantly reduces the layout area of current-mode DACs by the virtue of its compact size. The proposed DAC can replace the write driver circuits in phase change memories. Both 6-bit and 12-bit DACs have been fabricated in 0.5 mum CMOS technology. The layout size of the 12-bit and the 6-bit DACs is 0.09 mm 2 and 0.04 mm 2 respectively. Experimental results are presented and the limitations are discussed.