Search

To allow the use of molybdenum disulfide (MoS2) in mainstream Si CMOS manufacturing processes for improved future scaling, a novel MoS2 transistor with a 10-nm physical gate length created using a p-type doped Si fin as the back-gate electrode is presented. The fabrication technology of the ultra-small MoS2 device shows fully process compatibility with conventional Si-FinFET process flow and it is also the first time to realize the large-scale fabrication of the arrayed MoS2 transistors with 10-nm gate lengths. The fabricated ultrathin transistors, consisting of 10-nm gate length and 0.7-nm monolayer CVD MoS2, exhibit good switching characteristics and the average drain current on/off ratio reaches to over 106. This technology provides a promising approach for future CMOS scaling with large scale new 2-D material transistors.

A straightforward and fast (~200 µs) DCIV technique, which is completely compatible with the commercial semiconductor analyzer., is demonstrated to measure the time kinetics of interface trap generation (ΔN I T ) during and after DC/AC NBTI stress in Si p-FinFETs. The measurement time of each VG step in a staircase IV waveform can be down to 2 µs, It is found that the repassivation of ΔN IT after DC stress is a very fast process and happens within 200 µs recovery time. The delayed recovery phenomenon of ΔN IT is observed only for Mode-B AC stress and high frequency (f) Mode-A AC stress., resulting in the f-dependent ΔN IT under Mode-A AC stress and f-Independent ΔN IT under Mode-B AC stress.

Cold Source Field Effect Transistor (CSFET) enabled by source engineering is a promising candidate to achieve unique sub-60 mV/dec steep-slope switching. For the first time, we present an industry-standard multiscale TCAD framework for CSFET with proposed effective cold carrier distribution model, which captures the underlying physics of cold carrier injection efficiency, and carrier thermalization. The multiscale framework incorporates Non-Equilibrium Green’s Function (NEGF) simulations for validation. The effects of geometry configuration and source engineering are extensively investigated on a Si-based Double-Gate (DG) CSFET.

At present, the actual operation effect of some existing park-level integrated energy systems (PIES) is quite different from the initial target, and there are some weak links such as poor complementarity and coordination of certain units, the mismatch between energy supply and demand, and low consumption capacity of renewable energy. To effectively eliminate the weak links, identification of weak links and expanding capacity reconstruction technology for the PIES is proposed in this paper. First, mathematical models are built for each equipment of the PIES. Secondly, an identification method of weak links is established based on the operation data and the evaluation index system. On this basis, the expanding capacity reconstruction technology of the existing PIES is proposed, and the transformation scheme is solved by a mixed-integer linear programming algorithm. Finally, a case study is illustrated to verify the effectiveness of the technology proposed in this paper.

A comparative study is carried out to understand the defects in p-type ferroelectric FinFETs (FE-FinFETs) under negative bias temperature condition. Two types of traps, preexisting and generated ones, are unambiguously identified and their energy profiles are separated. Comparing with their Si-based counterpart, it is found that both devices exhibit similar pre-existing traps, however, generated traps in FE-FinFET show much weaker stress bias and temperature dependence due to suppressed bulk trap generation. The results suggest that the pre-existing traps are physically located within the SiO 2 interfacial layer (IL) while the bulk trap generation is mainly located in the high-k layer. The suppressed bulk trap generation process could be ascribed to Zirconium in the high-k dielectric, which might strengthen oxide bonds and suppress the generation of precursors of generated bulk traps.

We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses: (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions; (2) Kubo-greenwood model for low field mobility with considering surface roughness and stress; (3) multisub-band Boltzmann transport equation based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics; and (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5-nm node pMOS, and Si is still promising for nMOS due to strong quantum confinement in Ge channel.

In this work, high performance negative capacitance (NC) p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf 0.5 Zr 0.5 O 2 ) layer are fabricated based on a conventional high-κ metal gate (HKMG) FinFETs fabrication flow. The devices show improved drain induced barrier lowering (DIBL) and subthreshold swing (SS) values compared with those of conventional FinFETs with gate lengths (L G s) from 20 nm to 500 nm.

In this paper, a p-type tunnel field-effect transistor with source-pocket junction (SPTFET) has been presented. The source-pocket junction was formed at the interface between source and channel region using BF 2 high-angle implantation, which is helpful to reduce the tunneling distance and increase the carriers’ tunneling probability. Compared with the TFET without source-pocket junction, the fabricated SPTFET exhibits better electrical characteristics, such as large on-state current and small subthreshold swing.

After research, we find that the inner wheel difference has caused a large number of traffic accidents, and its harm cannot be ignored. In order to reduce traffic accidents, an Arduino-based warning device for inner wheel difference is designed in this paper. We first analyze the calculation model of inner wheel difference, then design and assemble each module separately based on the Arduino. In the visual warning part, the Single Shot MultiBox Detector (SSD) object detection model is used to locate and identify pedestrians and common objects, in order to realize a device for alerting both drivers and pedestrians based on vision and ultrasonic wave. Finally, based on the characteristics of the warning device and the social development, we analyze the advantages, technical feasibility and development prospects of the device.

In this paper, a biocompatible biosensor based on horizontal Si nanowire (NW) array field-effect transistor (FET) has been fabricated by the feasible spacer image transfer (SIT) process. The Si NW FET as biosensor is proposed for the realtime cellular Ca2+ monitoring for mesenchymal stem cells (MSCs), which presents fast-responded and high-sensitive characteristics. Compared with the conventional sensing techniques, the Si NW biosensor exhibits non-invasive, biocompatible and reliable advantages. This will help us to further understand the mechanism of cellular ion activities and provides a promising method for the cell-level diagnose and therapy.

For the first time, we experimentally demonstrated a 10nm node HfZrO based FE-FinFET device with both Charge Trapping and Domain Switching memory effect. Extreme high endurance (> 1012), high operation speed ( 10 years) and read disturbance immunity were achieved, showing great potential for e-NVM application.

In this paper, the relationship of Ni 0.86 Pt 0.14 -silicide film properties and the corresponding phase evolution is investigated extensively. We find that the Ni(Pt)-silicide phase transformation is often accompanied with greatly sheet resistance (R sh ) changes. However, Pt 3 Si peaks are detected when the R sh of Ni(Pt)-silicide starts to change from low resistance to high resistance. The Pt 3 Si phases maybe the transient phases, at a drastic Ni(Pt)-silicide phase transformation and crystal structure changes. The new Pt 3 Si phases would be transformed into a crystal structure similar to the new generating Ni x Si 1-x phase, which contribute to form a more stable and reliable Ni(Pt)-silicide film. A new model is proposed to interpret the new generated Pt 3 Si phase. The discovery contributes to a better understanding the role of Pt and control Ni(Pt)-silicide formation in future advanced devices.

In this paper, a fin-on-insulator (FOI) FinFET structure with a metallic source and drain (MSD) and HKMG-last processes was investigated extensively. FOI FinFETs demonstrated ten times of leakage current reduction compared with conventional bulk FinFET using p-n junction. In contrast to bulk FinFETs, MSD FOI FinFETs demonstrate a greatly improved control of short channel effects (SCEs) (∼47% DIBL and ∼32% SS reductions for 20-nm-Lg PMOS) compared to conventional bulk FinFET. The drive ability of 20-nm-Lg FOI transistor is increased about 30 times with full Ni(Pt) silicide process, up to 547 μA/μm for NMOS and 324 μA/μm for PMOS at V DD = 0.8 V. However, the excellent controls of SCEs and channel leakage were also obtained. No obvious increase of leakage happens in FOI FinFETs using fully Ni(5%Pt) silicide process.

A mixed lithography with self-aligned spacer image transfer (SIT) technology and I-Line lithography is successfully demonstrated in this paper. The large patterns are defined in the resist film through photolithography whereas the smaller patterns are defined through self-aligned SIT. The formed nanometer hard mask (HM) patterns have a good compatibility with I-Line lithography. The image transfer process by etching Si is further verified in our experiment. The mixed patterns with well uniformity after Si etching illustrate the feasibility and provide a useful candidate for the real needs in the future.

In this paper, some new developments of SOI and FOI (fin-on-insulator) FinFETs with conventional silicide S/D and Schottky barrier S/D are summarized. It is observed that large junction leakages occur for bulk FinFETs with conventional silicide S/D. By forming Ni(Pt)Si (5% Pt) silicide with conventional silicide process, parasitic resistances of FOI FinFETs are dramatically reduced without increasing of leakage currents and then device performance are increased significantly. An additional 50% performance enhancement is achieved for the FOI FinFETs with Schottky barrier S/D. The good controls of short channel effects and channel leakage are also obtained for FinFETs on insulator. High-k metal gate is used for the FinFETs.

The large parasitic resistance has become a critical limiting factor to on current (I ON ) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (R c s) and 55% reduction in sheet resistances (R s s) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (L g ) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

In this paper we develop an immersed interface finite element(IFE) method based on rectangular mesh for a kind of anisotropy diffusion models which is governed by an elliptic interface problem with discontinuous tensor-coefficients. The method is based on bilinear polynomials on non-interface rectangular elements and piecewise bilinear polynomials on interface rectangular elements. We prove that a function of the IFE space is uniquely determined by the values of vertices on the elements. Then, we construct the IFE space, define an IFE formulation and prove that the IFE formulation is uniquely solvable. At last, we obtain the optimal order H1 and L2 convergence results for the IFE solution, which are O(h) and O(h2) respectively.

Because of the rise of the use of solar energy resources, with the studies on the desert of solar power plant, this paper is aim at problem of design of the western desert solar power plant of bracket of solar module in Inner Mongolia Autonomous Region of China, starting with the design for each structure problem of bracket of desert plant photovoltaic panel, and then to conduct an overall analysis of ANSYS, and the finally compare with traditional bracket which has foundation from a single to a group to get the economy better and more popular desirable bracket to install solar module.

The solar energy resource of two typical areas was tested by taking advantage of different instruments from home and abroad in Inner Mongolia. Compared the actually tested data with satellite data from National Aeronautics and Space Administration, energy cost was estimated in different solar energy resource conditions through the use of RETScreen project analysis software form Canada. Analysis results show that acquisition of accurate data is the precondition of solar energy resource assessment and difference of solar energy resource assessment outcome will bring to important impact to energy cost.

Constructing of parabolic trough solar thermal power plant can provide scientific basis for future large scale application and industrialization evaluation in Inner Mongolia of China. Feasibility of constructing parabolic trough solar thermal power plant was analyzed in Inner Mongolia of China in this paper, and come to a conclusion that Inner Mongolia has the advantages such as solar energy, land, water, natural gas and electric network for constructing parabolic trough solar thermal power plant.