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Overvoltages related to shunt reactor switching is one of the most important phenomena that has challenged the operation of medium voltage circuit breakers. In the present article, the overvoltages caused by switching of shunt reactor by a 20kV vacuum circuit breaker (VCB) are investigated and some efficient solutions to control them are presented. This study was performed on a real power network and the results were presented for various considerations. Surge arresters and RC snubbers are the most common and efficient tools for controlling switching overvoltages. The use of these types of equipment in different conditions has been studied and compared with each other. This comparison has been performed in two cases with and without the phenomenon of multiple reignitions. For a more practical study, compliance with the requirements and related common standards is also included in this study. Also, the effect of the switching instant on the level of overvoltages and the phenomenon of multiple re-ignition has been investigated. Finally, according to the conclusions of various studies, a practical and appropriate solution for controlling overvoltages is introduced.

This paper presents a CMOS optical analog frontend for an implantable fluorescence biosensor for single-cell measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, ambient light and dark current canceling technique is proposed to make the sensor operate at different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is simulated at the post-layout level. The minimum integrated input-referred current noise is obtained as 546 fA at the average power consumption of $1 \mu \mathrm{W}$ for bandwidth (BW) of 1.4 kHz. For ultra-low-power configuration, the front-end has an average power consumption of 24 nW and input integrated current noise of 210 pA with 50 kHz BW.

This paper presents a $\mathrm{g}_{\mathrm{m}}$ -boosting noise canceled ultra-wide-band (UWB) low noise amplifier (LNA) topology to optimize the noise figure (NF) and power consumption of the well-known common gate (CG) topology. The $\mathrm{g}_{\mathrm{m}}$ -boosting voltage amplifier is implemented by a common source (CS) to achieve a higher transconductance, by the same bias current, in the CG stage. The next stage includes two paths to apply the noise canceling technique and finally another CG transistor at the output to sum up the produced currents of the second stage. The designed structure is simulated at the post-layout level by TSMC 90 nm RF-CMOS technology.

This paper presents an ultra-low-voltage ultra-wide-band (UWB) LNA utilizing forward body bias (FBB) technique. The designed structure consists of two common-sources and a bandwidth extending output buffer network. The adapted FBB technique decreases the amount of threshold voltage at both stages, which leads to a lower supply voltage, higher transconductance and yielding a reduction in the overall power consumption. The series-peaking inductor, Lm2, is aimed to boost the gain at high frequencies. The post-layout simulation results show 19±1.3 dB gain, 1.3-4.3 dB noise figure (NF) and less than −12.5 dB input return loss with a IIP3 of −5.5 dBm.

We apply computational-mathematical models to elucidate the brain's pattern recognition from music in tasks such as classification of music pieces according to style and historical period, such as Baroque, Classical and Romantic periods. We propose deep learning as the computational intelligence medium of choice to implement the model. The feasibility study reported below explores a special case to design an algorithm that could distinguish different styles of music, especially the Baroque music and the romantic music. The input is a piece of music, and the output will be the style of the music.

Baroque is a unique period for emergence of creative novelties in artistic ideas and technique improvement. Baroque art shows the influence of pre-Baroque period's humanism perspective, and it exerted an extraordinary influence on art following it. In the following, computational intelligence and deep learning are applied to elucidate the relationships among painting in the three periods. We outline the methodology and reports a successful preliminary study from limited data, which explored the concepts/techniques that have remained, or disappeared during the historical changes, and elucidated the connection among the Pre-Baroque, Baroque Period and Post-Baroque Periods.

Atmospheric Chemistry is important in public health. This paper highlights methodology aspects from analysis of atmospheric chemistry data in China, its correlation with cancer morbidity data, and impact on future cancer morbidity rate that are due to changes in climate.Forthcoming papers use DL for prediction. Research on cancer and analysis of cancer morbidity are provided by Liu Yuxin, Zhaorong Zhu [5].

In this paper we present our hardware architecture on a highly scalable, shared-memory, Monte-Carlo Tree Search (MCTS) based Blokus-Duo solver. In the proposed architecture each MCTS solver module contains a centralized MCTS controller which can also be implemented using soft-cores with a true dual-port access to a shared memory called main memory, and multitude number of MCTS engines each containing several simulation cores. Consequently, this highly flexible architecture guaranties the optimized performance of the solver regardless of the actual FPGA platform used. Our design has been inspired from parallel MCTS algorithms and is potentially capable of obtaining maximum possible parallelism from MCTS algorithm. On the other hand, in our design we combine MCTS with pruning heuristics to increase both the memory and LE utilizations. The results show that our architecture can run up to 50MHz on DE2-115 platform, where each Simulation core requires 11K LEs and MCTS controller requires 10KLEs.

In this paper an innovative T-Gate based Static Random Access Memory (SRAM) cell design is proposed which improves write-ability of conventional designs in subthreshold operating region. Write-ability of proposed design is improved by cutting the feedback loop in SRAM cell and omitting the challenging inverters effect during write state by adding a T-Gate. This T-Gate is opaque during write operation and transparent for rest of operations. Due to improved write operation, it is possible to choose minimum size access transistors to remove access transistor sizing conflict of conventional 6T SRAM cell. As a result, read stability will be improved. Added T-Gate in the middle of the cell helps to better transferring both of logic-1 and 0 that leads to having full swing at the internal nodes of SRAM cell. As a result leakage power of proposed cell is improved over the previous design introduced in [1]. Simulation results show that proposed design improves leakage power of single cell by 38% at T=110°C and at VDD=500mV over that design. WNM of proposed design is increased by 188% and 62% over the cell in [1] and conventional 6T SRAM cell, respectively.

High throughput AES encryption/decryption is a necessity for many of modern embedded systems. This article presents a high performance yet cost efficient AES system. Maestro can be used in a wide range of embedded applications with various requirements and limitations. Maestro is about one million times faster than the pure software implementation. The Maestro architecture is composed of two major components; the soft processor aimed at system initialization and control, and the hardware AES engine for high performance AES encryption/decryption. A ten stage implicit pipelined architecture is considered for the AES engine. Two novel techniques are proposed in design of AES engine which enable it to reach a throughput of 12.8 Gbps. First, tightly coupled encryption and round key generation units in encryption unit, and second, ahead of time round key generation in decryption unit. Altera DE2-115 development and educational FPGA board is used as the platform for Maestro. In the proposed architecture the DMA modules act as interfaces between data sources and data sinks by loading the input data into AES engine and taking encrypted and generated test data to target memories.

In the recent past there has been a lot of discussion in the pulp, paper and power industries regarding the recruitment of young engineers. There is a growing concern of a shrinking talent pool and a pending human resources crisis. There are several published papers that discuss strategies for educating and recruiting up and coming engineers. This paper, however, discusses the expectations and perspective on the job market from the point of view of recent engineering graduates. A survey was conducted of 30 near-graduate and recent graduates of various engineering disciplines asking their motivations for choosing their particular field. From experiences on a university campus, the most effective recruiters are those who actively go after students by: providing meaningful co-op/internship experience as well as by being involved with on-campus information sessions and events. Furthermore, the pulp & paper industry has unique challenges and opportunities with regard to adapting new technologies and the potential benefits to the environment. These attributes of the industry, if presented compellingly, can be used to more effectively attract young engineers.