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Convolutional neural networks have become the state of the art of machine learning for a vast set of applications, especially for image classification and object detection. There are several advantages to running inference on these models at the edge, including real-time performance and data privacy. The high computing and memory requirements of convolutional neural networks have been major obstacles to the broader deployment of CNNs on edge devices. Data quantization is an optimization method that reduces the number of bits used to represent weights and activations of a network model, minimizing storage requirements and computing complexity. Quantization can be applied at the layer level, by using different bit widths in different layers: this is called hybrid quantization. This article proposes a new efficient and configurable architecture for running CNNs with hybrid quantization in low-density Field-Programmable Gate Arrays (FPGAs) targeting edge devices. The architecture has been implemented on the Xilinx ZYNQ7020/45 devices and is running the AlexNet and VGG16 networks. Running AlexNet, the architecture has a throughput up to 508 images per second on the ZYNQ7020 device, and 1639 images per second on the ZYNQ7045 device. Considering VGG16, the architecture delivers up to 43 images per second on the ZYNQ7020 device, and 81 images per second on the ZYNQ7045 device. The proposed hybrid architecture achieves up to $13.7\times $ improvement in performance compared to state-of-the-art solutions, with small accuracy degradation.

Object detection and classification is an essential task of computer vision. A very efficient algorithm for detection and classification is YOLO (You Look Only Once). We consider hardware architectures to run YOLO in real-time on embedded platforms. Designing a new dedicated accelerator for each new version of YOLO is not feasible given the fast delivery of new versions. This work’s primary goal is to design a configurable and scalable core for creating specific object detection and classification systems based on YOLO, targeting embedded platforms. The core accelerates the execution of all the algorithm steps, including pre-processing, model inference and post-processing. It considers a fixed-point format, linearised activation functions, batch-normalisation, folding, and a hardware structure that exploits most of the available parallelism in CNN processing. The proposed core is configured for real-time execution of YOLOv3-Tiny and YOLOv4-Tiny, integrated into a RISC-V-based system-on-chip architecture and prototyped in an UltraScale XCKU040 FPGA (Field Programmable Gate Array). The solution achieves a performance of 32 and 31 frames per second for YOLOv3-Tiny and YOLOv4-Tiny, respectively, with a 16-bit fixed-point format. Compared to previous proposals, it improves the frame rate at a higher performance efficiency. The performance, area efficiency and configurability of the proposed core enable the fast development of real-time YOLO-based object detectors on embedded systems.

Blockchain is an emerging technology that has gained a lot of visibility in recent years due to its characteristics of transparency and immutability. Many studies have been carried out in order to use this technology in the financial industry, but there are still issues regarding scalability that need to be resolved before the technology can be used. In the literature there are works that perform Blockchain performance analysis of the private model, making comparisons between different platforms. However, no work was found regarding the analysis of the impact that changing parameters has on the performance of private model Blockchain applications. In this context, this article introduces PriBB that contributes to the literature regarding the proposal of a benchmark to evaluate the performance of private model Blockchain applications. In particular, it focuses on the impact that the parameters of block size and interval between blocks have on the performance of applications, since no equivalent work has been found in the literature. The PriBB was evaluated in a real data center environment and aims to assist in the optimization of parameterization of Blockchain applications of the private model. The results are promising and demonstrate that a given parameter can impact more than 100 times the performance in running Blockchain applications.

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

The idea of combining multiple CPU and CGRA cores is not in itself original but detailed characterizations of such architectures and measurements on compelling applications are difficult to find in the literature. Although commercial CPUs, GPUs and FPGAs are widely available, there are no commercial CGRAs, which may be attributed to the lack of metrics on performance, energy and cost. In this paper, we introduce a heterogeneous computing platform consisting of several RISC-V CPU and Versat CGRA cores. Implementation results for several instances of the architecture are presented. The CPU of choice is the promising open source RISC-V architecture, which has never been featured in CPU/CGRA architectures. This paper presents independent implementations of two RISC-V cores: a minimal one, useful as a simple controller, and a more performant 5-stage pipeline implementation. The RISC-V cores have been designed using the recent Chisel HDL, useful for automating tasks pertaining to the writing of RTL. The selected CGRA is the published Versat architecture, for which 4 different instances have been created. Implementation results for 2 FPGA families and ASIC technology nodes are presented: area, frequency and power. Applications cover digital audio and machine learning, demonstrating the versatility of the proposed platform at competitive area, frequency and energy footprints.

The continuous increase in the amounts of data received at the edges of the Grid is pushing the pre-computation of sensor data at the IoT device before communicating it over the network. Moreover, in the IoT context, devices are often required to operate under heavy power and area constraints and be subjected to harsh environments. However, in this context, traditional computing paradigms struggle to provide high availability and fault-tolerance. Stochastic Computing has emerged as a competitive computing paradigm that produces fast and compact implementations of arithmetic operations, while offering high levels of parallelism, and graceful degradation when in the presence of faults. Stochastic Computing is based on the computation of pseudo-random sequences of bits, hence requiring only a single bitstream per signal. In virtue of the granularity of the bitstreams, the bit-level specification of circuits, high-performance characteristics and reconfigurable capabilities, FPGAs are often adopted to implement and test such systems. This work presents a tool that takes a high-level specification and automatically creates a complete Stochastic Computing systems capable of interfacing analog sensors directly on the FPGA, and perform computations over the stochastic bitstreams. Moreover, the presented framework is also able to generate custom stochastic processing units, perform fault-tolerance tests, and report estimates on performance, resources and power. As a proof-of-concept, this paper presents two Machine Learning applications typical in the IoT context, implementing Karhunen-Loeve Transform for data compression and Neural Networks for classification.

Due to the computational complexity of Convolutional Neural Networks (CNNs), high performance platforms are generally considered for their execution. However, CNNs are very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication. In this paper, we propose an architecture for CNN inference (Lite-CNN) that can achieve high performance in low density FPGAs. Lite-CNN adopts a fixed-point representation for both neurons and weights, which was already shown to be sufficient for most CNNs. Also, with a simple and known dot product reorganization, the number of multiplications is reduced to half. We show implementation results for 8 bit fixed-point in a ZYNQ7020 and extrapolate for other larger FPGAs. Lite-CNN achieves 410 GOPs in a ZYNQ7020.

Nowadays, accessibility to the Internet has increased remarkably; and the use of devices such as smartphones, tablets, laptops, PCs currently allow people to access a wide variety of applications, among which are those that allow locating places such as hotels, hospitals, parks, restaurants, thus allowing quick access to information. The present work emphasizes applications that allow the geolocation and location of almost any site, presenting a solution, to the location of all specialized health centers in pediatrics and family medicine located in the city, either the closest to the location current, or a nearby alternative, so this paper describes the development of a web application that improves search and location services, through the use of GPS technology and implementation of the Google Maps API. In addition to the implementation of XML files and the 3 layers architecture so that the presentation of the data is faster and more dynamic for the user. All this following the development process presented by the Scrum methodology.

As technology develops, the demand for better tools are the order of the day, devices such as: Smartphone, tablets, laptops, PCs allow access to a wide variety of applications and services. The lack of a system that facilitates the georeferencing of beauty salons, which also traces the route from one point to another, and that allows to display information such as your exact address, style, gender, local references, etc. Realizing an investigation of the subject a custom application was created, using tools of last generation, such as: Language of Hypertext Marks 5, language of leaves of styles 3, programming language PHP, JavaScript, database MYSQL, Bootstrap, Bitbucket repository, unlike existing applications in the market this proposal raises: Registration of owners of hairdressers where the owner enters the system and can register, registration of hairdressers, also offers a filtering system of premises where the user can find your beauty salon so that you can classify them in two ways: customer service, that is, the beauty salon serves men, women, children, pets, and on the other hand the classification of the hairdressing salon, if it is modern, classic, casual, etc.

This document is, an overview of security problems and current systems to protect or insure a vehicle, because if it is not secured it can be a victim of vehicle theft that lately, although it has been decreasing, it is still valid. The proposal is to create a low-cost prototype to make the functions of vehicle safety control and location in case of loss to the end user can be informed according to the mobile platform that is provided.

Deep neural networks have recently shown great results in a vast set of image applications. The associated deep learning models are computationally very demanding and, therefore, several hardware solutions have been proposed to accelerate their computation. FPGAs have recently shown very good performances for these kind of applications and so it is considered a promising platform to accelerate the execution of deep learning algorithms. A common operation in these algorithms is multiply-accumulate (MACC) that is used to calculate dot-products. Since many dot products can be calculated in parallel, as long as memory bandwidth is available, it is very important to implement this operation very efficiently to increase the density of MACC units in an FPGA. In this paper, we propose an implementation of parallel MACC units in FPGA for dot-product operations with very high performance/area ratios using a mix of DSP blocks and LUTs. We consider fixed-point representations with 8 bits of size, but the method can be applied to other bit widths. The method allows us to achieve TOPs performances, even for low cost FPGAs.

Magnetic materials are broadly use in electrical engineering applications, due to its high permeability that allows increasing magnetic flux. Analyzing systems containing these magnetic cores is complex due to the nonlinear behavior of the magnetic material. This nonlinear behavior can be represented by the magnetization curve and by the hysteresis phenomenon curve. In this work, only magnetization curve is modelled and shows flow variations by varying the magnetic field. For higher values of magnetic field, there is not a present considerable variation of magnetic flux. At this stage, the magnetic material or the core reaches its saturation. In this work, simple mathematical models represent nonlinear behavior of magnetic material in order to be used in circuit simulation and inductor design. Linearized, polynomial and hyperbolic models are used. The linearized model approaches experimental BH curve for linear segments. The polynomial model approaches the curve by polynomial equation and the hyperbolic model approaches the curve using a hyperbolic equation. For models implementation is needed the experimental BH curve. An RL circuit is used. Equations of the electric circuit, magnetic flux and the material model are coupled and solved. To validate, simulation and experimental voltage and current are compared.

This article describes the infrastructure and architecture required for the implementation of an automation system for the current SIMERT Tariff Municipal System of Rotating Parking in the city of Loja. The best technological architecture was identified among the models of technological architectures based on web services as SOA, SOAP and REST. The required network infrastructure was specified in addition to both the user's and the centralized management system's applications, which will be used to manage parking times and fines for users. The goal is that the user has the facility to find a parking lot and dial the parking lot from his smartphone through a mobile application, thus eliminating the manual system of physical control cards, saving human resources that were necessary for the surveillance in the different streets where the manual rate system is located. Using the developed application will be an efficient management of the vehicles in use and real time of the parking system, controlling times and fines.

In the present project, a wireless connection (via Bluetooth) is made between a mobile device and a light control system, in order to manage the on and off of the domestic light. This application can be adapted to any electrical installation, only adding a Bluetooth touch panel, allowing the disabled people in the mobility, control the on and off of the lights of your home, regardless of where you are in your home, manage it from your own mobile device or from the touch panels installed in strategic places of your home. This application has been developed using the software autodesk circuit and bluetooth over Arduino, allowing this circuit can be managed or controlled from a mobile phone that has Android technology. In this way we take advantage of the advantages offered by the use of wireless connections (Bluetooth) in everyday life.

Global Positioning Systems (GPS) now provide great benefits for companies that need the location of a device or a point of interest. Today, smart mobile devices have increased exponentially by the features that these devices are able to offer thanks to their processing power. This document develops an application that provides a location service for university users, giving the facility to know the time of arrival of a bus from its current location to a previously established stop. Also defined is the methodology in the construction of the system, the REST architecture applied to the construction of the web service, which allowed to improve the performance of the application, which was created Android platform devices, allowing any mobile device to operate With this Operating System will be able to run the application and make use of it.

Harmonics and Quality of Power (ICHQP 2016) we welcome all delegates and visitors to Belo Horizonte. The International Conference on Harmonics and Quality of Power is one of the premier international conferences in the field and aims to provide a forum for electrical engineers and scientists to present their work and share information in this area of growing interest and importance in the Electric Power Industry around the world.

This paper proposes a novel fault-tolerant human-implantable artificial pancreas integrated circuit achieving high dependability. The main objective of this work is to provide fault-tolerance to this safety-critical application and extend its lifetime similar to existing techniques such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR). The key idea is to explore a hybrid-substrate with an FPGA-like fabric attached to an Application-Specific Integrated Circuit (ASIC) that leverages DMR on a per-module basis to detect transient and permanent faults and ASIC and FPGA-like reconfiguration for correcting faults. When fault-tolerance against permanent faults is considered, the proposed architecture has 5,100x lower failure rate per hour than DMR with 2.4x area overheads. In the case where transient fault protection is required, our approach achieves 83x lower failure rate per hour than TMR with 1.6x area overheads.

Stochastic computing has emerged as a computational paradigm that offers arithmetic operators with high-performance, compact implementations and robust to errors by producing approximate results. This work addresses two of the major limitations for its implementation which affects its accuracy: the correlation between stochastic bitstreams and the unobserved signal transitions. A novel implementation of stochastic arithmetic building-blocks is proposed to improve the quality of the results. It relies on Self-Timed Ring-Oscillators to produce different clock signals with different clock frequencies, by taking advantage of the influence of process variation in the timing of the logic elements on the FPGA. This work also presents an automated test platform for stochastic systems, which was used to evaluate the impact of the proposed enhancements. Tests were performed to compare both proposed and typical implementations, on reconfigurable devices with 28nm and 60nm fabrication processes. Finally, presented results demonstrate that the proposed architectures subjected to the impact of process variation improve the quality of the results.

Frequently, applications such as image and video processing rely on implementations of the Linear Projection algorithm with high throughput and low latency requirements. This work presents a framework to optimise Linear Projection designs that excel typical design implementations via a pre-characterisation of over-clocked arithmetic units. It is well known that the delay models used by synthesis tools are generic and tuned for the worst performance possible of a given fabrication process. Hence, they impose a heavy penalty in the possible maximum performance offered by the fabrication process. The proposed optimisation framework focuses on the optimisation of the generic multipliers, as they are the arithmetic operators with the most critical paths in the data path of a linear projection design, by performing a performance characterisation step on the target device. Experiments demonstrate that the proposed framework is able to generate Linear Projection designs that achieve higher throughput (up to 1.85 times) while producing less errors than typical implementation methodologies.

This paper presents the porting of the Ginga MiddleWare onto a Digital Television System-on-Chip. Ginga is an open-source software layer compliant to the Brazilian Digital Television Standard. The porting of Ginga is being carried out on a home made FPGA platform containing a Leon-3 processor running Linux, and the implemented audio and video decoders and graphics processing engine. The SoC has an external memory to store reference frames, OS and Ginga, user interface and applications with local and remote interactivity. Furthermore, accelerators are being designed to boost the SoC performance by implementing in hardware the most processor demanding Ginga primitives, with the profiling being made on a Ginga Virtual machine, therefore creating a “Ginga-Ready” platform.

Frequently, the high-level algorithm parameter selection and its mapping into hardware are considered to be independent processes, often leading to suboptimal solutions. When DSP applications with real-time constraints are targeted, it is often desirable the resulting hardware system to be clocked at as high frequency as possible. Even though the trend in modern devices is to provide a fabric that can support higher frequencies, its variability makes the design tools to be pessimistic about maximum clock frequency estimates. The proposed framework optimizes and mitigates the probabilistic behaviour of digital circuits, by trying to expose the impact of variability of the fabric into high-level algorithmic specifications. FPGAs are well positioned to tackle this problem because they can be reconfigured, allowing an off-line characterization of the specific device before implementing the complete optimized circuit on the same device. Circuits generated by the proposed framework outperform typical implementations, by minimizing area, errors, and maximizing its operating clock frequency. An example of a linear projection circuit, over-clocked by 232%, shows savings up to 39% in hardware resources for the same target PSNR over traditional implementation.

The aim of this paper is to analyze the additional electrical losses in resistors subjected to non-ideal conditions of operation, ie, harmonic currents. With respect to the traditional ways to calculate the additional losses question, the analysis presented in this work is done in order to differentiate an increase of losses due to an increase in the RMS value and due to the current distortion waveform. Thus, in this paper, this analysis is based on both computer simulations and in laboratory measurements of the resistor temperature. The results from these two analysis tools are compared and confronted each other.