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In this article, we propose a monitoring procedure based on a multilayer neural network with multivalued neurons (MLMVN) capable of preventing catastrophic failures of dc–dc converters. The neural classifier allows both the detection of any malfunction and its localization. Thanks to the low computational complexity, the proposed method operates online, estimating the deviations of the passive components from their nominal values: this allows control strategies to be promptly adopted and operation of the dc–dc converter to be kept in high efficiency and reliability conditions. Since measuring the voltage and current on each component increases the complexity of the system, a testability analysis is proposed with the aim of identifying the minimum number of measurements needed to distinguish the classes of failure. To make the testability phase easier and more intuitive, a graphical representation is proposed. As a case study, prognostic analysis has been applied to prevent catastrophic failures in a synchronous Zeta converter. Several fault conditions have been analyzed through simulations and experimental tests. The obtained results confirm the ability of the proposed method to prevent failures and, also, show that the application of MLMVN results in a better performance than classic solutions available in the literature, such as support vector machine. [ABSTRACT FROM AUTHOR]

This paper presents an effective approach to the fault diagnosis of pulsewidth modulated (PWM) DC–DC power converters. It is based on a multilayer multivalued neuron neural network with a complex QR decomposition. This network is used to identify the parameter values running out of tolerance range in two topologies of PWM DC–DC converters, namely, the buck and boost circuits. The proposed technique is based on measurements of steady-state voltages and currents waveforms. [ABSTRACT FROM AUTHOR]

Testability analysis is a fundamental prerequisite to any fault location or parameter identification technique (FLPIT) for analog circuits. However, differently from the linear time-invariant field, this topic has been poorly investigated with regard to nonlinear circuits. In this paper, for the first time, to the best of our knowledge, the question is addressed with reference to periodically switched networks with dc stimuli (PSNDSs), a class of inherently nonlinear time-varying circuits that subsumes dc-dc converters as noteworthy members. A rigorous testability measure at both a circuit and a component level is thereby obtained, which provides information as to how many and which components can be unambiguously diagnosed or estimated from time-domain measurements. Consequently, it yields an upper bound, independent of the parameter values and the test instants, to the performance of whatever method actually employed as an FLPIT. This theoretical testability metric has been converted into an efficient computer program for the fully automated testability analysis of PSNDSs presented herein. Such a computer program represents the first practical testability gauge for PSNDSs: it can be employed by both test engineers and circuit designers as a guide to properly selecting injection and measurement points as well as estimating the number of necessary measurement instants, so as to shape their own FLPITs. Several examples are provided for which an in-depth pencil-and-paper testability analysis is contrasted with its automated counterpart provided by the aforementioned software: in particular, popular dc-dc converter topologies are thoroughly analyzed. Comparisons with a previously proposed frequency-domain testability measure are also considered. [ABSTRACT FROM PUBLISHER]

A new procedure for the selection of test frequencies in the parametric fault diagnosis of analog circuits is presented. It is based on the evaluation of algebraic indices, as the condition number and the norm of the inverse, of a sensitivity matrix of the circuit under test. This matrix is obtained starting from the testability analysis of the circuit. A Test Index (T.I.) that permits the selection of the set of frequencies that better leads to locating parametric faults in analog circuits is defined. By exploiting symbolic analysis techniques, a program that implements the proposed procedure has been developed. It yields the requested set of frequencies by means of an optimization procedure based on a genetic algorithm that minimizes the T.I. Examples of the application of the proposed procedure are also included. [ABSTRACT FROM AUTHOR]

Presents an efficient approach for ambiguity group determination in low-testability analog linear circuits. Basis of the approach on the use of the singular-value decomposition of the testability matrix of the circuit under test; Characteristic of the approach; Development of a program implementing the proposed method.