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The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnects subject to Direct-Current (DC) EM stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. The proposed test structure features a ring-based Voltage-Controlled-Oscillator (VCO), a bit-pattern generator and local BER sampling monitors which enable bitwise tracking of ‘0’ and ‘1’ errors separately, further simplifying the overall test-setup and allowing for high precision characterization of EM induced resistance shifts using only digital circuits. Measurement data collected from the 16nm prototype reveals unique insights into EM induced signal path degradation that was not available prior to this work. Our experimental studies suggest that monitoring the BER of an interconnect path could be used as a new metric for capturing EM induced resistance shifts in a real system, in lieu of the conventional approach which focuses on monitoring standalone wire resistances. Supplemental simulations showcasing the projected degradation in the interconnect path operating frequency as a function of stress time constructed from resistance traces sampled from identical wires implemented in the same process reaffirm the measurement trends. [ABSTRACT FROM AUTHOR]

This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages ($V_{\mathrm {TH}}$), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD, $V_{\mathrm {TH}}$ , device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types. [ABSTRACT FROM AUTHOR]

This article presents neutron radiation-induced soft error rate (SER) statistics and detailed analysis thereof, revealing a multitude of circuit parameters impacting the soft-error susceptibility of standard combinational logic in advanced CMOS nodes. A high-density array-based soft-error characterization vehicle is presented, featuring standard logic gate chains of varying lengths. Neutron irradiation data obtained from gate variants employing devices with distinct channel widths and threshold voltage flavors is analyzed at multiple supply voltages, ranging from nominal down to near-threshold. Supplemented with first-order simulations, measured SER cross-section results obtained from test structures implemented in a 65-nm planar CMOS technology node reveal the complex interplay between factors, such as supply voltage, node capacitance, restore current (IRESTORE), gate topology, and logic chain length responsible in contributing toward the collective soft error susceptibility of a standard gate type, which constitutes the main focus of this article. In addition, the easy process portability of the proposed macro is demonstrated through implementation in a 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC. [ABSTRACT FROM AUTHOR]