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Power electronics have been widely used in the transmission systems due to its capability to control the power flows as well as the voltages and currents. However, in the renewable energy transmission system, the weak-grid will make the VSCs work under nonlinear domain, where their behavior are quite different from the linear case. What's more, the interconnected VSCs are sometimes used to ensure more robust and flexible power transmission, leading to a multi-machine system, where the predominant nonlinear oscillations should be studied to suggest more information in designing the parameters of the system. This paper proposed a methodology to offer analytical results to predict nonlinear interaction for both oscillation amplitude and frequency-shift while avoiding numerical simulation of huge computational burden. Based on Normal Form theory, this methodology can be applied to large-scale power system that exhibits behavior of N coupled second-order oscillators. The nonlinear indices are then proposed to quantify the parameter impact on the nonlinear system dynamics.

The increase of renewable energy sources and HVDC links lead to power systems composed of a large number of interconnected Voltage Source Converters, involving predominant nonlinear oscillations. The strong coupling effect in the severely stressed system obscures the characteristics of the nonlinear dynamics. To tackle this problem, a proposed Nonlinear Mode method based on Normal Form theory makes possible to decompose the system modeled by N coupled nonlinear damped oscillators into a sum of decoupled nonlinear damped oscillators, keeping the physical meaning along with reducing the complexity of the problem. Mode decomposition and amplitude-dependent frequency-shift are then extracted, rendering a deeper insight of the system dynamics possible. The efficiency of the method is illustrated by a simple but didactic case-study.

This paper investigates the design architecture and the optimum resistance state values for high-endurance, high-yield energy-efficient OxRAM-based non-volatile flip-flops (NVFF) for ultra-low power applications in 28nm FD-SOI. Silicon measurements demonstrate that a low programming current improves endurance, but at the expense of a reduced memory window (R OFF /R ON ). Statistical analyses show that the scaling limitation of the NVFF operating voltage in restore mode can be overcome with a narrow memory window by using a current-based design solution. Low variability of the FD-SOI enables to operate down-to 0.7V with more than 108 of endurance cycles.

Enabling high speed SRAM operation at low voltage is typically limited by variability and low device drivability. Most of the reported low-voltage SRAM bitcells show significant area penalty and low performances. This paper proposes a Mixed-Single Well (MSW) 8T SRAM bitcell, which takes advantage of wide back bias voltage range capability of ultra-thin body and box (UTBB) FD-SOI technology The bitcell is evaluated in 28nm using the read-after-write (RAW) dynamic metric which overcomes the limitations of standard readability (RA) and writeability (WA) approaches. It is demonstrated that body biasing tuning enables operation of the proposed bitcell at approx. 5.6s at 0.4V with over 100MHz.

Emerging connected devices operating on battery or harvested energy sources highlight the need for ultra-low standby power design. Including non-volatility in flip-flops (FF) allows nullifying the power consumption in sleep mode, while maintaining the system state. Most of the reported solutions require FF modifications while increasing their complexity. This paper presents a non-volatile flip-flop (NVFF) designed as an OxRAM-based pulsed latch tied to a regular FF for ultra-wide voltage range applications. In 28nm CMOS FDSOI, adding non-volatility cut-off the FF leakage at the cost of 63pJ of data store and restore energy and less than 15% of delay penalty.

Improving SRAM minimum operating voltage (V min ) in scaled process nodes requires characterization of different failure mechanisms. Persistent errors caused by random variations and intermittent errors caused by random telegraph noise (RTN) both contribute to bitcell failure. Random V th shift was measured for 32,000 in-situ SRAM cells in both 28nm bulk and FDSOI processes due to both random variations and RTN, and dynamic writeability was measured by two different write modes that accentuate different RTN behaviour. Measured distribution parameters of both random variation and RTN were used to calibrate an accelerated Monte Carlo simulation that predicts a V min difference due to RTN. Measurements show that while FDSOI technology reduces random variation by approximately 27% compared to bulk, similar RTN amplitudes slightly increase bitcell susceptibility to failures caused by RTN.

A novel hybrid memory architecture - Non-Volatile SRAMs (NVSRAMs) wherein resistive memories incorporated as an integral part of SRAM cell to provide information back-up feature is presented in this paper. It also makes a discussion on some of the challenges faced in implementing hybrid memories and the prospective solutions.

Passive stress sensors have been integrated in a silicon interposer test vehicle to investigate thermo-mechanical stress in a typical 2.5D system. The present sensors are integrated in a rosette-shape consisting of eight oriented copper serpentines acting like strain gauges. An innovative design allows theoretically the calculation of a partial stress tensor, including three planar and one out-of-plane components. Electrical measurements at wafer level, combined to FIB/SEM cross-sections, revealed a strong impact of elaboration processes on the structures electrical characteristics. Numerical siumations using finite element analysis were built to evaluated the theoretical sensitivity of copper serpentine to mechanical strains. Finally a dedicated four-point bending tool coupled with a four-terminal resistance measurement setup was fabricated to extract experimentally the values of sensors sensitivity factors. Preliminary results depicted in this paper highlight a sensitivity to stress of distinctly oriented resistors. Several identified sources of data dispersion are inherent to the present measurement configuration and prevent a reliable calculation of strain gauges so-called “gauge factors”.

This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.

This paper presents a predictive analysis of the high-density SRAM cell scaling from the stability and low power perspective. Based on a subthreshold SRAM analytical model [5] and a SRAM area-scaling model the Data Retention Voltage (DRV) defined as the lowest VDD that can be applied during standby without losing data, as well as the minimum supply voltage for reliable read and write (VMIN), are investigated. The analysis is performed for several future technology nodes down to the 18 nm node. It takes into account the impact of MOS key parameters: threshold voltage (VT), subthreshold slope, DIBL, body factor and Pelgrom's Coefficient AVT. It is demonstrated, that due to process variations, the use of bulk CMOS for sub-28 nm becomes very challenging and severely limits area and supply scaling. Thin-film technology such as Ultra-Thin Body and BOX (UTBB) FDSOI however, should allow stable and power- and area-efficient SRAM design scaling below the 22 nm node with DRV lower than 0.4 V.

This work investigates the effects of process variability on the dynamic stability of a 6-Transistor Static Random Access Memory bitcell manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) technology node. The study is carried out for two different well architectures: single-well (peculiar to UTBB-FDSOI) and dual-well (like in standard CMOS), through Most-Probable Failure Point tracking methodology coupled with Importance Sampling. Different failure mechanisms appearing under different operating conditions are discussed. We show that the Read-After-Write failure criterion based on multiple Word-Line pulses is the most accurate way to evaluate bitcell failure rate and thus its yield under realistic dynamic conditions. The methodology exposed in this work is applied to demonstrate the superior properties of the single-well architecture.

This paper presents an overview of the design challenges and solutions under development for Nano-scale technologies. Major applications requirements and nano-technologies design limitations are introduced. Adaptive techniques aiming to cope with variations and to track an optimal energy operating point are presented.

Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar bulk CMOS. At 28nm, we find that planar FD more than matches the peak performance of “G”-type bulk technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. FD implementation of a representative design offers 1.6×–7× speedup compared to bulk across a range of supply voltages.

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is proposed to allow high quality 3-D layout generation. Our experiments demonstrate the effectiveness of CELONCEL technique, fetching us an area gain of 37.5%, 15.51% reduction in wirelength, and 13.49% improvement in overall delay, compared with a 2-D case when benchmarked across an interconnect dominated low-densityparity-check (LDPC) decoder at 45nm technology node.

We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data on both mobility and electrical figures of merit (device and SRAM) offers major opportunities for predictive design based on TCAD simulations.

International audience; This paper presents an universal optimization model for Static Noise Margin (SNM) of Ultra Low Power (ULP) CMOS SRAMs in the presence of statistical variations. Distributions of retention and read SNM derived analytically, are analyzed as a function of the threshold voltages of the N and PMOS devices. The proposed model implemented in Matlab is applied to optimize yield by maximizing the mean/6σ of SNM in the presence of local statistical VT variation of 3σ.

This paper presents a new SRAM memory cell in Double Gate MOS technology. It’s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (δ/μµ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.

This paper presents an innovative 6T SRAM cell designed in Monolithic 3D IC technology. A specific compact model in 45nm has been developed haled on silicon measurements and TCAD extractions. The simulation results exhibit a strong improvement of the cell electrical characteristics thanks to the ability to modulate the threshold voltage of the devices (static noise margin +10%, number of bit per line +12%, static power consumption −12%), when compared with a standard 6T cell designed in 2D. The cell layouts, designed with 45nm SRAM rules in 2D and 3D, show a 20% area gain.

In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45nm technology node. The stability of the cell reaches 20% of V DD and the cell leakage is 13pA. A minimum cell area of 0.209µm2 with specific 45nm SRAM design rules has been reached. This is 16% smaller than the smallest 6T SRAM cell reported in 45nm Bulk technology. Moreover, the proposed cell displays a good manufacturability. It is a cost saving process because it requires only one GP doping, no substrate contact at the cell level and is based on a conventional FDSOI process flow.

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF ( 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology. Promising results in term of density and stability using TCAD simulations are shown for a 4T SRAM load-less cell.

This paper investigates leakage reduction techniques for a conventional 6T SRAM cell in advanced technologies. The most promising leakage reduction techniques that have been proposed are presented and compared for the 130-nm and 65-nm technology nodes. More specifically, the impact of the evolution of the gate tunneling and substrate currents is studied considering the efficiency of those techniques. Finally, the best techniques for leakage reduction in sub 100-nm SRAM cell, and guidelines on how to merge them in order to reach an optimum, are proposed.

This paper presents silicon characterization results of various power gating techniques in a 0.13mum low power PD-SOI technology. A standby leakage current comparison is performed for floating body, body contacted and DTMOS transistors. It is shown that sleep transistors composed of PMOS in DTMOS configuration with an increased channel length are the best devices to reduce leakage power consumption in standby mode. Furthermore, on one hand, SOI helps reducing dynamic power consumption by more than 40% compared to bulk, and on the other hand, by implementing leakage reduction techniques, the standby leakage power is lowered by one decade