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The long-term absence of organic drive management circuits has prevented organic integration from achieving full flexibility. The high off-state breakdown performance and its avalanche-like breakdown mechanism of copolymer Organic Semiconductor (OSC)-based Organic Field Effect Transistors (OFETs) have been revealed in recent researches. By employing diketopyrrolopyrrole-based conjugated copolymer OSC(DPPT-TT) as the semiconductor layer and Polymethyl methacrylate(PMMA) as the dielectric/passivation layer, the H-bridge circuit can be fabricated with four OFETs integrated on the same Corning glass substrate. The non-destructive avalanche-like breakdown mechanism provides the power OFET a 300 V high BV(Breakdown Voltage), whose critical electric field excesses 5 MV/cm. The fabricated devices also demonstrated the high current density more than 121 A/cm2 and field-effect mobility up to 0.22 cm2/( $\text{V}\cdot \text{s}$ ). The top-gate bottom-contact structure allows the fabricated OFETs a high on-state current density and good device stability without using package construction or other special isolation techniques. By connecting resistors and LEDs on the load side of the H-bridge circuit made of $63~\mu \text{m}$ channel devices, measurement results show that it has good driving effects and driving performance. These measured results show that organic power devices are a potential candidate for application in the power realm.

A facile and damage-free patterning pro- cess was proposed to solve the incompatibility in the traditional photolithography process by introducing graphene oxide (GO) as a protective layer for poly (3,4-ethylenedioxythiophene): polystyrene (PEDOT:PSS) film. As a result, a high-resolution GO/PEDOT:PSS elec- trode array with a feature size down to $3 ~\mu \text{m}$ was fabricated. Moreover, the PEDOT:PSS films exhibit average optical transparency up to 92.6% in the visible light range, excellent conductivity (~2000 S cm−1), and high conformability. Based on the GO/PEDOT:PSS electrode array, the confor- mal organic field-effect transistors with the highest mobility of up to 1.4 cm $^{{2}}\,\,\text{V}^{-{1}}\,\,\text{s}^{-{1}}$ and average mobility of 0.83 cm $^{\vphantom {\text {D}^{\text {j}}}{2}}\,\,\text{V}^{-{1}}\,\,\text{s}^{-{1}}$ by layer-by-layer lamination were successfully fabricated. Our process was highly compatible with traditional photolithographic patterning techniques, which may provide a route for the integration of complex soft electronics. [ABSTRACT FROM AUTHOR]

Self-heating (SH) is a phenomenon that can induce excessive heat inside the transistor channel. SH represents an emerging and serious concern, especially in advanced technology nodes, where excessive heat acting on elevated channel geometries will notably shift the critical transistor parameters (e.g., threshold-voltage $V_{\text {th}}$ and carrier mobility $\mu $). The underlying 3-D device structures (e.g., FinFET, nanowire, or nanosheet structures), along with newly employed materials such as silicon-germanium (SiGe), which show worse thermal conductivity than traditional materials, can considerably exacerbate SH. On top of that, quantum confinement, a phenomenon that becomes dominant at sub-10nm, further increases the intensity of SH. In this article, we are the first to explore SH effects from the perspective of hardware security, rather than the performance, reliability standpoints covered in state-of-the-art (SOTA) work. As proof of concept, we devise an SH-based hardware trojan (HT) that exploits the SH-induced $V_{\text {th}}$ change in 7-nm FinFET circuits. Leveraging $V_{\text {th}}$ -dependent reconfigurable logic, we design a reconfigurable HT payload that maliciously changes its functional behavior once the SH-induced $V_{\text {th}}$ change takes effect. Following SOTA work, we present a comprehensive modeling and analysis of SH effects at the device level and highlight its impact on transistor $V_{\text {th}}$. Next, we study how fabrication-time changes in the transistor doping and geometry can promote the SH-assisted degradation. We then describe various payload configurations for the proposed HT, quantify its overheads, and discuss its resilience against standard HT detection techniques. Finally, we demonstrate two case studies using the proposed HT, one to leak the secret key from a pipelined design of an advanced encryption standard (AES) circuit, and another to showcase denial-of-service for a Gaussian-blur filter circuit. Our work utilizes industry-standard models with parameters extracted from measurements and calibrated with experiments. Our results are obtained from meticulous study and optimization across the device-, circuit-, and system-levels. [ABSTRACT FROM AUTHOR]

Developing the multi-valued logic circuits, that can handle more data than the conventional binary logic circuits, is a promising strategy to break through the well-known Moore’s law. In this letter, we demonstrate quaternary logic circuits, for the first time, based on the four-level organic thin-film transistor nonvolatile memories (OTFT-NVMs) as the core components. High-performance four-level OTFT-NVMs are achieved, with the low programming/erasing voltages of ±15 V, high mobility up to 7.4 cm2/Vs, reliable endurance, and stable retention capabilities. By connecting the four-level OTFT-NVMs with a load resistance in the reasonable ways, we build the logic circuits to reliably perform quaternary logic operations of NOT, NAND and NOR, respectively. Our works lay the foundation to develop the novel quaternary integrated circuits in hardware. [ABSTRACT FROM AUTHOR]

We report solid-phase crystallization (SPC) of amorphous silicon (a-Si) using blue laser annealing (BLA) and its application to thin film transistor (TFT). The a-Si film on glass was crystallized by exposure of blue laser for short duration of $50~\mu \text{s}$. The temperature of Si increases up to ~1100 °C and induces fast SPC. A 100 nm poly-Si on glass has full width at half maximum of Raman intensity 5.53 cm−1 and atomic force microscopy (AFM) root mean square surface roughness of 1.18 nm, indicating high quality poly-Si with smooth surface morphology without grain boundary. The coplanar SPC TFT using BLA exhibits the field effect mobility of ~27.0 cm2 / $\text{V}\cdot \text{s}$ , on/off current ratio of >107 and excellent stability. [ABSTRACT FROM AUTHOR]

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of $27.7~\mu \text{A}/ \mu \text{m}$ at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor. [ABSTRACT FROM AUTHOR]

Introducing a negative transconductance (NTC) regime into a switching curve of a field-effect transistor is a promising approach to overcome the fundamental limit of traditional digital logic circuits. However, the operation of NTC devices is only weakly conceptualized up to the present. This study proposes a drastically new way of regarding an NTC transistor as a functional equivalent of three interconnected normal field-effect transistors. The electrical model is directly inspired by the structural and materials characteristics of high-performance organic devices, and it is fully confirmed by measured experimental data. This finding, therefore, rationalizes that the NTC transistors have a unique potential to greatly reduce the transistor count in an integrated circuit, and offers a simple yet universal tool for systematic design and optimization of NTC transistor circuits through simulation-driven engineering. [ABSTRACT FROM AUTHOR]

Flexible organic field-effect transistors (OFETs) based on solution-processed TIPS-Pentacene as semiconductor and high- ${k}$ P(VDF-TrFE) gate dielectric are successfully demonstrated on fabric for future electronic textile (e-textile) applications. These devices exhibited very high electrical performance with maximum ($\mu _{{\mathrm {max}}}$) and average ($\mu _{{\mathrm {avg}}}$) field-effect mobility values of ~1.2 and ~0.5(±0.3) ${\mathrm {cm}}^{2}\cdot {\mathrm {V}}^{-1}\cdot {\mathrm {s}}^{-1}$ , respectively, in the saturation regime and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of ~103 for a low operating voltage of −5 V, along with excellent electromechanical stability. Furthermore, these devices showed excellent environmental stability with almost unchanged electrical characteristics for 26 weeks. Moreover, devices showed high cyclic stability with stable ON/ OFF switching characterized up to 500 cycles. [ABSTRACT FROM AUTHOR]

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe2/SnSe2 van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe2/metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance. [ABSTRACT FROM AUTHOR]

Cross-linking polymer gate dielectric is an efficient strategy to improve its intrinsic properties for high-performance flexible organic field-effect transistors (OFETs). However, the detail optimization process of the polymer films with the various cross-linking degrees is often ignored, which can bring a significant effect on the electrical performance of OFETs. In this work, the cross-linked poly (vinylalcohol) (CPVA) is introduced as the gate dielectrics for the high-performance ultraflexible OFETs. The dielectric property and the surface property of CPVA thin films with various cross-linking degrees are investigated in detail. The OFETs with a high average mobility of 7.3 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ , a current ON/ OFF ratio of over 107, and a lower density of trap states of $8.7\times10$ 11 eV $^{-1}\cdot cm^{-2}$ are achieved successfully. Moreover, the ultraflexible OFET presents a high mobility of over 5.1 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ even bending around a copper wire with a small radius of $400 ~\mu \text{m}$ , due to the ultrathin thickness of the device. These results demonstrate that the CPVA thin film is a promising candidate dielectric material for flexible organic transistors, presenting huge potential for the next-generation flexible electronic devices. [ABSTRACT FROM AUTHOR]

The low-field hole mobility in p-type inversion-mode silicon (Si) and germanium (Ge) nanosheet (NS) transistors is rigorously calculated by a physics-based theoretical model, where momentum scatterings from phonons, charged impurities, and surface roughness are all considered. With a holistic physical picture of carrier scattering mechanisms, the effects of material, crystal orientation, channel width, strain/stress, and temperature are investigated comprehensively by the in-house developed numerical simulator. This sound and prospective theoretical work paves the way for clarifying the physics of achieving high hole mobility in ultrascaled NS channels, presenting some valuable insights and guidelines about the device design and fabrication for the next-generation CMOS technology. [ABSTRACT FROM AUTHOR]

The effect of contact gating is studied in high-performance, dual-gated, single-layer (1L) WS2 MOSFETs with semi-metallic Bi contacts. Using a dual-gate geometry, we study the contribution of contact gating in lowering contact resistance, ${R}_{C}$ , by changing the top-gate and bottom-gate voltages independently. The ${R}_{C}$ of the bottom-gated biasing configuration shows ~20x lower contact resistance than the top-gated biasing configuration. ${R}_{C}$ is shown to be strongly affected by the bottom gate voltage, even at fixed channel carrier concentration, and this dependence is shown to be related to modulation of the transfer length by the bottom gate. The results show that despite the importance of semi-metallic materials in improving contact resistance, contact gating is still necessary to achieve ultra-low contact resistance. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) responses are investigated for 3-D-sequentially integrated fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Strong layer-to-layer coupling of TID response is observed. The simultaneous application of positive bias to the gate of the bottom-layer device and negative bias to the top-layer device leads to the maximum enhancement of positive charge trapping in the top-layer device and the intermediate dielectric layer. This enhancement is due to the upward-directed electric field in the intermediate dielectric layer under these bias conditions. In contrast, electrostatic shielding prevents the gate bias of the top-layer device from affecting the response of the bottom-layer device, as confirmed by experiments and technology computer-aided design (TCAD) simulations. Effects of layer-to-layer coupling are less significant for postirradiation-biased annealing. [ABSTRACT FROM AUTHOR]

Conventional bulk silicon is approaching its physical limit in the continued scaling of field-effect transistors (FETs). To extend the scaling limit of silicon-FETs, 2-D silicon semiconductors are highly desired because of the atomic thickness and mature CMOS-compatibility. By employing the hybrid honeycomb-kagome (hhk)-silicene monolayer as transport channel, we study the performance of sub-5-nm p- and n-type FETs based on ab initio quantum transport simulations. The hhk-silicene pFET (nFET) can be scaled down to 2-nm (3 nm) gate length (${L}_{g}$) with performances fulfilling the high-performance requirements of International Technology Roadmap for Semiconductors (ITRS) for 2028 horizon. Besides, with ${L}_{g}$ scales down to 3 nm, the subthreshold swing (SS) of the hhk-silicene FETs still can break the thermal limit of 60 mV/dec. The subthermal switches of hhk-silicene FETs benefit from the relatively isolated bands near the Fermi level. This work reveals the great potentials of hhk-silicene for ultrascaled and steep-slope FETs in future. [ABSTRACT FROM AUTHOR]

The artificial neural networks based on biomimetic synaptic devices attempts to process and memorize information by simulating a human brain. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices, due to their large specific capacitance, low operating voltage, and sensitive interfacial properties. Although large-scale EGTs array based on inorganic electrolytes and small-scale EGTs arrays based on organic electrolytes are reported, large-scale EGTs arrays based on organic electrolytes have not yet been focused. In this work, a large-scale EGTs array ($10\times10$) based on coplanar-gate structure using lignin as electrolyte is fabricated. The organic dielectric layer fabricated in the last step can be protected from the damage caused by wet etching, thus providing an opportunity for the application of other organic electrolytes in the large-scale EGTs array. Lignin exhibits good electric performance and is environment-friendly due to its renewable property. The synaptic properties of single transistor in the EGTs array, such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass filtering are realized. The real-time learning and forgetting procedures stimulated by different spike numbers of EGTs array are also demonstrated. [ABSTRACT FROM AUTHOR]

Amorphous indium–gallium–zinc oxide (a-IGZO) is a promising channel material for an upper transistor in monolithic three-dimensional devices. Although the field-effect transistors (FETs) with a rather thick channel thickness >10 nm have been intensively examined, less information is available for the IGZO FETs with an ultra-thin body (< 10 nm). In this study, the FETs with the IGZO channel layer ranging from 2 to 20 nm were investigated in detail. As the channel thickness decreased from 20 to 7 nm, the mobility and subthreshold swing (SS) values were improved. In contrast, the deterioration in mobility and SS occurred when the IGZO thickness was less than 7 nm. The physical rationale for the strong IGZO thickness dependence on performance of the resultant FETs was discussed based on subgap density-of-state distribution and mobility models such as percolation and surface-roughness scattering mechanisms using a technological computer-aided design simulation with a quantum mechanical model. IGZO FET with an IGZO thickness of 7 nm exhibited the best performance, which was attributed to the synergic balance by percolation efficiency and reduction in effective subgap defect density of IGZO. [ABSTRACT FROM AUTHOR]

In order to comply with the rapid development of new-generation electronics, developing memories which could meet the demands for specific application such as flexibility, transparency and neuromorphic functions are of great significance. In this work, a transparent organic nonvolatile memory (transparency≥81%) is developed with Ag nanowire as floating gate layer, which exhibits excellent memory characteristics and mechanical flexibility. Moreover, the transition from memory to artificial synapse is achieved by adjusting the concentration of Ag nanowire. This work provides a new solution for transparent flexible memory and shows their potential for next-generation transparent organic electronics. [ABSTRACT FROM AUTHOR]

In this article, the interface trap-assisted ferroelectric polarization in ferroelectric-gate field effect transistors (FeFETs) is investigated based on technology computer-aided design (TCAD) simulations. The metal–ferroelectric–metal (MFM) capacitors and FeFETs are fabricated to reflect ferroelectric and device model parameters to the simulations. By introducing interface traps between ferroelectric layer and Interlayer (FE/IL) and implementing the charge trapping through nonlocal tunneling model, it is revealed that the trapped charges at the FE/IL interface enhance the polarization of the FE, and they determine a memory window (MW) by the compensation between the polarization enhancement and the trapping-induced threshold voltage shift. Furthermore, the effects of the remaining trapped charges depending on a trap relaxation on the MW are rigorously analyzed by monitoring the transient changes of the polarization and the trapped charges in pulse program/read operations. [ABSTRACT FROM AUTHOR]

Artificial synaptic devices have been developed to simulate biological synapses, while the connections in different synapses are different in strength, which is usually ignored in current research of artificial synapses. Here, we develop organic synaptic transistor array in a single wafer using inkjet-printing to simulate synaptic behavior with one presynaptic membrane and multiple postsynaptic membranes. By regulating droplet spacing during inkjet-printing, synaptic array with varying synaptic behavior can be achieved. This new type of synaptic transistor array enriches the diversity of neuromorphic devices and provides a new direction for the construction of next-generation neural networks. [ABSTRACT FROM AUTHOR]

The solution-processed inverted co-planar organic thin film transistor (OTFT) incorporating recessed source-drain-gate and polymer gate dielectric is demonstrated to realize a fully recessed device. The impact of recessed electrodes on the contact resistance ($R_{c}$) and the mobility ($\mu $) is thoroughly investigated by comparing the performance of fully recessed devices, partially recessed (source-drain) devices and standard non-recessed devices. A reduction in $R_{c}$ by two orders of magnitude and 3-fold increase in $\mu $ to attain the values of $60 k\Omega $ - $cm$ (without any surface treatment) and $1.5\times 10^{-2}cm^{2}/Vs$ respectively are achieved in a fully recessed device as compared to the standard non-recessed device. [ABSTRACT FROM AUTHOR]

The electronic properties of a field-effect transistor with two different structures of MoSi2N4 and WSi2N4 monolayers as the channel material in the presence of biaxial strain are investigated. The band structures show that these compounds are semiconductors with an indirect bandgap. Their band gaps can be adjusted by applying in- plane biaxial strain. In the following, the variation of the energies of the valleys and corresponding effective masses with respect to the strain are explored. Finally, the strained MoSi2N4 or WSi2N4 are used as the channel of a p-type FET and the corresponding current–voltage characteristic is explored. The results show that this FET has an ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio larger than 106 and sub-threshold swing (SS) in the range of 96–98 mV/dec. The ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of these compounds with respect to strain are compared. [ABSTRACT FROM AUTHOR]

Transistors operating at high frequencies are the basic building blocks of millimeter-wave communication and sensor systems. The high charge-carrier mobility and saturation velocity in graphene can open way for ultra-fast field-effect transistors with a performance even better than what can be achieved with III-V-based semiconductors. However, the progress of high-speed graphene transistors has been hampered by fabrication issues, influence of adjacent materials, and self-heating effects. Here, we report on the improved performance of graphene field-effect transistors (GFETs) obtained by using a diamond substrate. An extrinsic maximum frequency of oscillation ${f}_{{\mathrm {max}}}$ of up to 54 GHz was obtained for a gate length of 500 nm. Furthermore, the high thermal conductivity of diamond provides an efficient heat-sink, and the relatively high optical phonon energy of diamond contributes to an increased charge-carrier saturation velocity in the graphene channel. Moreover, we show that GFETs on diamond exhibit excellent scaling behavior for different gate lengths. These results promise that the GFET-on-diamond technology has the potential of reaching sub-terahertz frequency performance. [ABSTRACT FROM AUTHOR]

The application of organic field-effect transistors (OFETs) in the power device realm has not been explored yet. To achieve a high breakdown voltage, a novel lateral drift region OFET(LDR-OFET) is proposed in this letter. By employing the diketopyrrolopyrrole-based polymer(DPPT-TT) and Poly (methyl methacrylate) (PMMA) to form semiconductor and insulator layers respectively, the fabricated LDR-OFET, despite the simple process and low cost, exhibits an excellent off-state breakdown capability while maintaining a considerable on-state performance. With a $20~\mu \text{m}$ length of the drift region, the LDR-OFET realizes 2200V breakdown voltage on a spin-coated 50nm thick semiconductor layer. The average electric field of the proposed device reaches 1.18MV/cm before an avalanche-like breakdown occurs. The physical nature of the breakdown mechanism is explored using the 1-D PIN equivalent structure and avalanche breakdown theory. The correctness and effectiveness of the proposed LDR-OFET and breakdown analysis are well demonstrated and validated by experimental results. The LDR-OFETs are expected to fill the blank of organic power devices and be the core component of future organic power integrated circuits. [ABSTRACT FROM AUTHOR]

An organic field-effect transistor nonvolatile memory with multibit storage capability and selective UV response was demonstrated, which showed good retention for all the memory states. The programming/erasing of the device operating at a low voltage was enabled by solar-blind UV light of 254 nm, and it had no response to 365 nm UV light and visible light. The stepwise switching between the memory states was controlled only by the number of the programming/erasing pulses, rather than by programming/erasing voltage or duration. The multibit memory feature is ascribed to the cumulative and reversible charge trapping in the employed polymer electret layer, and this architecture may offer a promising approach to multibit organic-based memories. [ABSTRACT FROM AUTHOR]

In this letter, organic thin-film transistors (OTFTs) with various interface modification conditions are fabricated and characterized. In addition to chemically homogeneous dielectric surfaces to enhance electrical characteristics of devices, morphologically homogeneous surfaces are also needed to achieve good device-to-device uniformity of OTFTs. The different charge trap densities at the dielectric interface and in pentacene film is responsible. [ABSTRACT FROM AUTHOR]

Logic-in-memory (LIM) technology is an important technology that overcomes the bottleneck, a limitation of the von Neumann architecture. As described in previous reports, the LIM technology was fabricated with a resistive load inverter structure. However, there are some limitations due to the high-power consumption issue and low noise margin. As a result, the need for a LIM device with a complementary structure has emerged. Here, we propose a LIM architecture-based organic-inorganic complementary inverter circuit with a stable noise margin using a p-type floating-gate transistor memory (FGTM) and an n-type zinc-tin oxide (ZTO) thin-film transistor (TFT). We demonstrate that the output of the proposed complementary inverter circuit is determined according to the state of the FGTM memory. [ABSTRACT FROM AUTHOR]

We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on 2-D materials. The electrostatics along the electrolyte-gated 2-D-semiconductor stack is treated by solving the Poisson equation, including the site-binding model and the Gouy–Chapman–Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2)-based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations. [ABSTRACT FROM AUTHOR]

A complementary vacuum field emission device structure is proposed, and its operation is analyzed by multiphysics simulation. A freely moving double-clamped cantilever, which balances the electrostatic attraction force and elastic restoration force, is used as the source electrode while the drain electrode is fixed. The electron-emitting cathode is formed on the source for the n-type device and on the drain for the p-type. Thus, complementary current–voltage characteristics are obtained only with Fowler–Nordheim tunneling electron transport. The impact of various design parameters such as vacuum gap, cantilever beam thickness, gate width, and tip offset on the drain and gate leakage currents is investigated. Inverter logic operation is verified successfully using complementary devices. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as the gate insulator are being extensively explored as a promising device candidate for non-volatile memory application. FE HfO2 exhibits long retention over ten years, high endurance over 1012 cycles, high speed with subnanosecond polarization switching, and high remnant polarization of 10– $30~\mu \text{C}$ /cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with Metal/Ferroelectric/Dielectric/Semiconductor (M/FE/DE/S) gate-stack is studied. It is found that the ferroelectric/dielectric (FE/DE) interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood. [ABSTRACT FROM AUTHOR]

We examine the electrostatic discharge (ESD) behavior of bottom-gate bottom-contact pentacene organic field-effect transistor (OFET) devices with a parylene-C gate dielectric. A comparison between devices with gate and contact overlap geometries of −2 to $3~\mu \text{m}$ are analyzed. In particular, the relationship between contact overlap, the protective effect of the increased overlap, and the electric field in the dielectric and their effect on ESD resilience is detailed. We find a markedly increased tolerance for negative contact overlaps and a small decrease in tolerance for more positive overlaps. We also report on a highly resilient effect where OFET devices continue to operate but with a reduction in performance after multiple dielectric breakdown. A negative overlap length should be carefully considered when designing OFET devices in a tradeoff between decreased performance and higher ESD resilience. [ABSTRACT FROM AUTHOR]

Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM is desired to capture the nonlinear device electronic characteristics and their high-order derivatives. However, for the novel devices in advanced and future technologies, establishing TCM based on analytical equations and extracting model parameters becomes tedious. The model fitting capability for device outputs’ high-order derivatives is also limited. These drawbacks hinder fast and accurate device to circuit evaluation cycles. We develop a TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework. This MNN model is able to simultaneously capture the transistor dc/ac characteristics, such as ${I}-{V}/{Q}-{V}$ , their derivatives (${G}-{V}/{C}-{V}$), and higher order derivatives accurately. Moreover, the model architecture can be widely adapted to various device types. Based on this model scheme, software is developed to enable the automated model generation for standard SPICE simulation. Finally, the model and software are validated for novel gate-all-around (GAA) Si cold source field-effect transistors (CSFET), and 19-stage ring oscillator and two-stage operational amplifier circuit simulations have also been demonstrated. This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours. In addition, it enables more precise circuit simulation for analog and RF circuits, and it provides a rapid solution for early stage design technology cooptimization (DTCO). [ABSTRACT FROM AUTHOR]

Neuromorphic computing, with information sensing, processing, and storage capabilities, is driving the development of a new generation of artificial intelligence (AI). Photonic synaptic devices are essential components for improving information processing efficiency owing to their advantages of a high propagation speed, low latency, and large bandwidth. In this study, a photonic synaptic transistor simply based on p-type organic semiconductor blending with n-type organic semiconductor was fabricated via simple solution process in which only light was used to control the enhancement and inhibition of the synaptic conductance. The device can simulate fundamental synaptic properties. Additionally, the coordination between light stimulation and electrical stimulation was investigated, and the results show that light-pulse stimulation is beneficial for increasing the response current simulated by electrical pulses. This work represents a significant step towards the realization of high-efficiency AI electronics. [ABSTRACT FROM AUTHOR]

A low-cost portable gas sensing system for the detection of eugenol in clove oil is described in this article. The sensor has been developed on a molecularly imprinted polymer (MIP) modified quartz crystal microbalance (QCM) platform. The system has two parts: 1) MIP-QCM sensor and 2) sensor signal measuring unit, which includes a crystal oscillator (10 MHz), a frequency counter (ATmega328P microcontroller unit), a liquid crystal display (LCD), and a data storage unit. A 10-MHz AT cut quartz crystal was coated with the synthesized solution of the optimum ratio of styrene, methyl methacrylate, and divinylbenzene with eugenol as the template. A crystal oscillator based on a simple complementary metal–oxide–semiconductor inverter and ATmega328 microcontroller were used for data generation and transfer. The portable instrument was used for the detection of eugenol in clove oil samples, which revealed reasonably good repeatability (96.37%), reproducibility (92.92%), and fast response time of about 1 min. The system could detect the concentration of eugenol at ppm level in different real samples. Finally, the response of the proposed system was correlated with the response obtained from gas chromatograph. [ABSTRACT FROM AUTHOR]

Low mobility and high operating voltages are bottlenecks in the practical application of ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memory (NVM). In this article, we demonstrate a high-mobility polymer semiconductor-based Fe-OFET NVM that can well operate at low programming/erasing voltages (VP/VE). The issue that hinders the reduction of the VP/VE in Fe-OFET NVMs is discussed. We develop a route to resolve the issue by building a thin bilayer gate insulator consisted of an ultrathin poly(methyl methacrylate) (PMMA) and a thin poly(vinylidenefluoride-trifluoroethylene) films. The processing compatibility, that is, the tri-layered core architecture consisting of polymer semiconductor and insulator films is prepared by a full-solution technology, is confirmed. The mechanism of the performance improvements by using the ultrathin PMMA in the Fe-OFET NVMs is investigated. As a result, the Fe-OFET NVM exhibits excellent performances at low VP/VE of ±15 V, with a high mobility up to 1.75 cm2/Vs, reliable memory endurance over 400 cycles, and stable memory retention over 65000 s. [ABSTRACT FROM AUTHOR]

P-type tin monoxide (SnO) thin-film phototransistors were developed with high photoresponsivity of $2.94\times 10^{{5}}$ A/W and high detectivity of $1.82\times 10^{{14}}$ Jones, and these values are, to the best of our knowledge, among the highest for the reported oxide-semiconductor-based phototransistors. The excellent performances of these phototransistors were further demonstrated by incorporating the devices into a ${10}\times {10}$ array to successfully image a letter “A” pattern. Furthermore, by integration of n-type indium gallium zinc oxide and p-type SnO thin-film phototransistors, we realized a complementary photosensitive inverter. The inverter exhibits excellent photoresponse with a high voltage gain rate change of 194%. Our results indicates that the SnO based phototransistors have great potential in thin-film photoelectronic circuits and systems. [ABSTRACT FROM AUTHOR]

In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation. Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising. Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching. In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications. Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance. Here, we demonstrate good device properties even for highly scaled devices (100 nm × 100 nm). [ABSTRACT FROM AUTHOR]

Electrospinning one-dimensional (1-D) semiconductor nanofibers have been regarded as one of the most promising building blocks for future nanoelectronics with high performance because they can exhibit a broad range of device functions. However, electronic devices based on electrospinning-driven nanofibers often suffer from poor performance and inferior quality. In current works, continuous and uniform high-quality indium oxide (In2O3) nanofibers were obtained by electrospinning. The surface morphology, crystallinity, optical, and electrical properties of the In2O3 nanofibers were investigated by X-ray diffraction, scanning electron microscopy, optical spectroscopy, and electrical measurements. It has been detected that the field-effect transistors (FETs) with optimized electrospinning time of 30 s demonstrated superior electrical performance, including a high field-effect mobility (μFE) of 9.1 cm2 ⋅ V−1 ⋅ s−1 and a large ION/IOFF of 107. The high- k Al2O3 dielectric layer has also been used to greatly reduce the operating voltage (from 30 to 3 V), significantly improve μFE (to 27.7 cm2 ⋅ V−1 ⋅ s−1), and strengthen stability over cycling. To prove the device’s potential in more complex logic circuit applications, a resistor-loaded inverter was further integrated, and the maximum voltage gain of 9.8 was demonstrated at an ultralow operating voltage of 3 V. The present findings have demonstrated that electrospinning can potentially be used as a straightforward and cost-effective means for the assembly of 1-D nanostructures for use in next-generation low-power devices. [ABSTRACT FROM AUTHOR]

The organic field-effect transistors (OFETs) have developed rapidly in recent years. However, compared with the p-type OFETs, the n-type devices always show poorer performance due to their hard electron injection and low stability. It is necessary to further improve the charge injection properties of n-type OFETs. In this work, indium (In) layers, as an interlayer above contacts, were adopted for electron injection improvement in the n-type poly((N, N'-bis(2-octyldodecyl)-1,4,5,8-naphthalenedicarboximide-2,6-diyl)-alt-5, 5'-(2, 2'-bithiophene)) (N2200) OFETs. The injection barrier, such as Schottky barrier, at the metal/semiconductor interface was effectively weakened with the In interlayers thickness (TIn) increasing from 0 to 6 nm. The mechanism of electron injection changed from thermionic emission to tunneling, as the TIn reaching 6 nm. It results in a marked improvement in electrical properties for N2200 OFETs. The mobility increased from 0.09 to 0.29 cm2 ⋅ V−1 ⋅ s−1 while the subthreshold swing decreased from 2.7 to 0.8 V ⋅ dec−1 with the TIn. This work provides an efficient approach for the electron injection improvement in n-type OFETs. [ABSTRACT FROM AUTHOR]

A thin film transistor (TFT) model applicable to circuit design is presented. The model is based on a general solution of the vertical 1-D Poisson equation, valid for asymmetric and independent top and bottom gates and for doped semiconductor films, with no restrictive approximations. The solution is necessarily numerical, but we describe a discretization strategy on a reduced and highly nonuniform grid, resulting in a computationally efficient model. The resulting long-channel model is complemented with empirical short-channel effect corrections. The model results are validated against measured c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) MOSFET data. [ABSTRACT FROM AUTHOR]

A through-plastic-via (TPV) three-dimensional (3D) integration approach is developed to integrate the organic field effect transistor (OFET) circuitry and the sensing/reference electrodes (SE/RE) for flexible bio-chemical sensor chips. Based on this approach, the SE can be fabricated using optimal processes on a different plastic substrate without concern of affecting the OFET part. Taking H+ detection as a proof-of-concept, it is demonstrated that a weak ion response (~7 mV induced by 0.2 pH) is amplified by 10 times through an integrated OFET common source amplifier. With close integration of the OFET amplifier and the SE, external noise influence can also be suppressed, beneficial for improving signal-to-noise ratio and improving the detection limit. [ABSTRACT FROM AUTHOR]

The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current–voltage and charge–voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities. [ABSTRACT FROM AUTHOR]

Ion gel-based dielectrics have long been considered for enabling low-voltage operation in printed thin-film transistors (TFTs), but their compatibility with in-place printing (a streamlined, direct-write printing approach where devices never leave the printer mid- or post-process) remains unexplored. Here, we demonstrate a simple and rapid 4-step in-place printing procedure for producing low-voltage electrolyte-gated carbon nanotube (CNT) thin-film transistors at low temperature (80 °C). This process consists of the use of polymer-wrapped CNT inks for printed channels, silver nanowire inks for printed electrodes, and imidazolium-based ion gel inks for printed gate dielectrics. We find that the efficacy of rinsing CNT films and printing an ion gel in-place is optimized using an elevated platen temperature (as opposed to external rinsing or post-process annealing), where resultant devices exhibited on/off-current ratios exceeding 103, mobilities exceeding 10 cm2V−1s−1, and gate hysteresis of only 0.1 V. Additionally, devices were tested under mechanical strain and long-term bias, showing exceptional flexibility and electrochemical stability over the course of 14-hour bias tests. The findings presented here widen the potential scope of print-in-place (PIP) devices and reveal new avenues of investigation for the improvement of bias stress stability in electrolyte-gated transistors. [ABSTRACT FROM AUTHOR]

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiOxNy) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures. [ABSTRACT FROM AUTHOR]

We study the effect of Gaussian energetic disorder on the organic field-effect transistors (OFETs) with surprisingly high field-effect mobility and the low contact resistance. The numerical device simulation assumes the thermally assisted hopping transport and injection in disordered semiconductors. The results are analyzed with the power-law field-effect mobility and the asymptotic power-law contact resistance model. Transistor parameters extracted by the models reveal that a higher Gaussian disorder, which leads to a lower injection barrier and a larger mobility enhancement, is the origin of the high field-effect mobility and the low contact resistance. [ABSTRACT FROM AUTHOR]

In this article, we present a computational investigation on nanoscale coaxial-gate negative-capacitance carbon nanotube field-effect transistor (NC CNTFET). The proposed nanodevice is endowed with metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. The simulation approach is based on solving self-consistently the nonequilibrium Green’s function formalism with the NC FET electrostatics considering ballistic transport conditions. The computational assessment includes the switching performance and short-channel effects (SCEs) in NC CNTFETs. The negative capacitance behavior of the ferroelectric has been found efficient in boosting the performance of nanoscale CNTFETs in terms of subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON-current, current ratio, and intrinsic delay. In addition, we show the capability of MFMIS configuration in improving the current ratio and SS of CNTFETs with ultrascaled gate lengths. The role of the ferroelectric layer thickness in enhancing the NC CNTFET performance is also studied, where improved performance has been recorded using thicker ferroelectric layer. Achieving high ION/IOFF current ratio, sub-kT SS, and improved immunity against SCEs makes the NC CNTFET as a potential candidate for modern CNT-based nanoelectronics. [ABSTRACT FROM AUTHOR]

One-dimensional metal-oxide nanowire networks (NNs) are considered as important elements in electronics due to their unique physical and electrical performances. In this letter, Sn1-x Gax O NNs were fabricated and field-effect transistors (FETs) based on Sn1-x Gax O NNs with different Sn/Ga ratios were constructed. The characteristics of the FETs have been systematically investigated. In order to promote the adhesion and electrical performance of nanowires, Sn1-x Gax O NNs were welded by introducing the polymer mixture containing poly vinyl pyrrolidone and poly methyl methacrylate. Utilizing a welding process, the transport properties of Sn1-x Gax O NNs have been greatly promoted, and the FETs based on Sn0.8 Ga0.2 O NNs exhibit optimum electrical performance. Once integrated with high-k ZrOx dielectric, the FET based on Sn0.8 Ga0.2 O NNs/ZrOx exhibits high stability and high electrical performance, including $\text{a}\mu _{\text{FE}}$ of 5.2 cm2 /V s, an $\text{I}_{\text{on}} /\text{I}_{\text{off}}$ of $1.5\times 10 ^{6}$ , a subthreshold voltage of 170 mV/decade, an on voltage of −0.25 V, and a negligible hysteresis of ~0.12 V. The successful fabrication of the FETs based on Sn0.8 Ga0.2 O NNs lays the foundation for the development of low-consumption, low-cost and high-performance electronic devices. [ABSTRACT FROM AUTHOR]

In this study, we propose a polysilicon (poly-Si) channel thin-film synaptic transistor based on an organic-inorganic hybrid electric-double-layer (EDL) structured gate dielectric. To implement the hybrid EDLs, which play a key role in artificial synaptic transistors, a protonic mobile ion-based bio-inspired chitosan electrolyte and a high- ${k}$ Ta2O5 dielectric thin-film were applied. Synaptic modulation was realized on the poly-Si channels by the polarization reaction of mobile protonic ions in the organic chitosan electrolyte. The chemically and mechanically stable inorganic Ta2O5 dielectric capping layer prevented deterioration of the organic electrolyte due to the patterning and etching processes, enabling the fabrication of large-scale integrated circuits. The fabricated EDL field-effect transistors (FETs) verified essential synaptic behavior. Therefore, polarization and depolarization in EDLs, paired-pulse facilitation, and excitatory post-synaptic current modulation were successfully emulated by applying pre-synaptic stimulation spikes. As a result, the proposed CMOS-compatible poly-Si thin-film synaptic FETs based on hybrid EDLs are suitable for emerging neuromorphic systems and compact artificial neural networks. [ABSTRACT FROM AUTHOR]

Previous methods of making metal-oxide electric-double-layer transistors (EDLTs) usually require a combination of different vacuum- or solution-based deposition techniques. Recent work has shown that sputtering offers another possibility to prepare oxide proton-conducting dielectrics for metal-oxide EDLTs. In this work, aluminum oxide proton-conducting dielectric is deposited by the dc reactive sputtering method, which helps the fabrication of fully metal-oxide EDLTs only with the sputtering technique. Humidity dependence of the obtained metal-oxide EDLTs is studied. It is found that humidity is a critical factor influencing the electrical characteristics. The underlying mechanism of humidity dependence is analyzed. Encapsulation of the device with polymer is demonstrated to provide basic isolation from humidity variation and stabilize the device. [ABSTRACT FROM AUTHOR]

Chemical doping is widely used in the electronic devices. In p-type semiconductor thin films, oxygen doping fills the hole traps and increases hole concentrations, improving the performance of the organic field-effect transistors (OFETs). Due to the low ionization potential for p-type semiconductors, the superfluous holes induced by the oxygen doping degrades the OFETs off-state leakage performance. On the other hand, for p-type semiconductors with high ionization potential (up to 5.5-6.0 eV), the limited oxidation of oxygen is hard to achieve satisfactory doping concentrations to fill the trap states. This refers to the well-known intrinsic incompatibility between the oxygen doping and high-performance OFETs. Herein, a novel strategy is introduced to overcome the incompatibility and achieve high-performance OFETs by using the structural polymer electret. That is, moderate hole concentrations induced by low-pressure (30 Pa) oxygen plasma fill the hole traps within semiconductor. And the built-in field resulted from polymer electret accumulates the holes inside semiconductor near the semiconductor/electret interface, thus improving the OFETs performance. Using a model organic semiconductor with high ionization potential-2,7-didodecyl[1]benzothieno [3,2-b][1]benzothiophene (C12-BTBT) as an example, the high-performance OFETs with field-effect mobility ($\mu _{FET}$) of 3.5 cm2V−1 s−1, subthreshold-swing (SS) of 110 mV decade−1, on-off ratio of 104, and widely-tunable threshold voltage (${V} _{t}$) are realized at a low voltage below 2 V in the open air. [ABSTRACT FROM AUTHOR]