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1. Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

4. Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below

5. First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP

6. Buried Power Rail Metal exploration towards the 1 nm Node

7. Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations

9. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

10. Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck

11. Toward successful integration of gap-filling ultralow-k dielectrics

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