Search

RRAM with multilevel resistance states of HfO 2 /Al 2 O 3 /HfO 2 based memristor on transparent ITO electrode is presented. Trilayer structure proves to be promising for multilevel memory state under DC voltage condition. Under different SET current compliance and RESET voltage the memristor device shows reliable multi-level resistive switching characteristics.

The Continuous Valued Number System (CVNS) is a new approach in computer arithmetic to develop high performance and efficient arithmetic units. In this paper, CVNS-based computation scheme is applied to design a memristive analog adder and it has been demonstrated that this technique is a viable alternative approach to implement multidigit arithmetic system with multilevel memory devices. The proposed CVNS adder has addition and modulo configurations to perform CVNS addition. A mapping circuit has been designed for modulo operation. The proposed memristive CVNS-based adder has been simulated and analyzed for different CVNS values with radix-10 and 2-digit analog environment resolution. The simulations are shown acceptable accuracy and the presented system performance promises an analog memristive computation method for future in-memory computation systems.

ReRAM (Resistive Random Access Memory) has been drawing attention for its neural network applications with low-power and high-speed operation. The multilevel data storage capability is inherently needed to use the ReRAM as synaptic devices. In this study, two ReRAM devices with different electrode materials in which the operation mechanisms are thought to be different was fabricated and tested. It was clarified that the multilevel resistance characteristics were achieved in both devices.

The novel approach to functional verification of memory subsystem components of multicore microprocessors with multilevel memory organization are considered in this paper. Some benefits of application standalone simulation based verification are marked out. The approach is based on application of high-level memory subsystem model of microprocessor full-system simulator. It allows to build UVM based test system and do not develop reference model of the verified unit. The architecture of the test system and functions of its components are presented. The memory subsystem model with the build-in checker could help to find bugs during the simulation. The memory subsystem model of Elbrus microprocessor and the test system for L2-cache verification are described.

In this paper, we present a novel co-existed bipolar/unipolar RRAM for high performance multilevel memory application. Good multilevel data storage characteristics are obtained in this TaTiN/HfO x /Pt based RRAM. Furthermore, based on switching characteristics of this RRAM, a novel operation mode is proposed to simplify the multilevel operation and optimize the device characteristics.

A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.

A new multistable circuit used to memorize currents is proposed in this work. A flash A/D converter operating in current mode has been designed to implement multilevel memories. The circuit has been fabricated in a 0.8/spl mu/m CMOS technology.

Multilevel dynamic storage employing refreshing schemes potentially allows very compact synapses with fast read and write operations. A circuit implementation is described which performs an 8-b to 10-b transmission of dynamically stored value and a 2-MHz, successive approximation, A/D to D/A (analog-to-digital to digital-to-analog) conversion. The synapse size is 105 mu m*75 mu m for a 2- mu m process. This implementation is capable of bandwidths in the low megahertz (1 to 20 MHz). >

VLSI constraints affect hardware electronic neural systems. Some architectural modifications are discussed. Hardware implementation of neural networks is required to achieve real-time performance. The architecture is dominated by the size and performance of the synapse, and therefore its design is critical to a dense neural architecture. The major problem in designing an analog synapse is the development of an analog memory. Several possible analog memories have been proposed, but for many applications, dynamic refreshing schemes allow the best overall performance. Dynamic refreshing schemes potentially allow very compact synapses with fast read and write operations. The system presented employs a very dense synapse that allows dynamic refreshing of 8 to 10 bit accuracy with a 1 mu s refresh/read time using a 2-MHz, successive approximation, analog/digital-digital/analog converter. The synapse size is 95 mu m*70 mu m for a 2 mu m process. >