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Spiking neural networks (SNNs) more closely mimic the human brain than artificial neural networks (ANNs). For SNNs, time-to-first-spike (TTFS) encoding, which represents the output values of neurons based on the timing of a single spike, has been proposed as a promising model to reduce power consumption. Adversarial attacks that can lead ANNs to misrecognize images have been reported in many studies. However, the characteristics of TTFS-based SNNs trained using a backpropagation algorithm against adversarial attacks have not yet been clarified. In particular, the dependence of the robustness against adversarial attacks on spike timings has not been investigated. In this brief, we investigated the robustness of SNNs against adversarial attacks and compared it with that of an ANN. We found that SNNs trained with the appropriate temporal penalty settings are more robust against adversarial images than ANNs. [ABSTRACT FROM AUTHOR]

This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase of power, several SNR and SFDR enhancement techniques are proposed. Firstly, the ADC repeats comparison of LSB by using redundant DAC to average comparator noise and improve SNR. The technique also corrects settling error adaptively, which extends operation speed to 50 MHz even though extra comparison period is added for averaging. Secondly, simple filtering method for reducing DAC noise is introduced to achieve further improvement of SNR. Finally, new dithering method is proposed to enhance SFDR. Injecting noise-shaped, multi-valued and uniform-distributed dither to input of the ADC, spurs caused by capacitance mismatches of DAC can be suppressed more effectively compared with conventional dithering. These techniques can be realized by simple circuits in addition to a basic SAR ADC configuration and do not need high power consumption. The chip is fabricated in a 90 nm CMOS process and occupies 0.1 mm 2 including all correction logic. The ADC achieved a peak figure of merit (FoM) of 168.7 dB. [ABSTRACT FROM AUTHOR]

An 11-b 300-MS/s double sampling pipelined ADC with on-chip digital calibration for memory effects is presented. In double-sampling pipelined ADC architecture, memory effect of residual charge occurs due to sharing an op-amp between two channels of pipelined ADC. The proposed foreground calibration technique removes the memory effect error in digital domain without additional analog circuit. Thus, the technique simplifies the analog circuits, which extends the operation speed over 300∼MHz. The chip is fabricated in a 40 nm CMOS and occupies 0.42 mm^2 including digital calibration logic. The ADC consumes 40 mW from a 1.8 V supply, and FoM is 0.24-pJ/conversion-step. [ABSTRACT FROM AUTHOR]

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (KV,) and charge-pump (CP) current over C (ICP/C), the SSCG can realize not only adaptive band-width but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using KV and ICP/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 118.6 dB which is 2.3 dB better than the reduction obtained without calibration. [ABSTRACT FROM AUTHOR]

A practical method for coupled oscillator design is elaborated. The topology analysis of a coupled oscillator, the ways of simulating its sensitivity, initializing its operation, and the oscillation frequency enhancement with nMOS phase couplers are presented. We have developed a write strategy system for DVD with a coupled oscillator using these techniques. In addition, we have also developed a low-power-oriented multiphase generator for mobile phones with our newly devised multiphase level shift system (M-LS). The M-LS has established superiority in its low power consumption because of no short current. Moreover, we have applied the method of output phase-accuracy improvement using a resistor ring to the M-LS. Two test chips are fabricated and the design method is validated. The first coupled oscillator has a resolution of 32 Ps and a phase accuracy of -1.0 to 0.8 LSB at 490 MHz, corresponding to 16 × DVD write speed. The second one consumes 1 mA and has a high phase accuracy of 0.5 LSB at 123 MHz. [ABSTRACT FROM AUTHOR]

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G[sub m]-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10[sup -6] of bit-error rate (BER) is obtained for the focus offset margins over ±0.5 µm. This SoC is fabricated in 0.13-µm one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm² die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode. [ABSTRACT FROM AUTHOR]

Presents information on a study which described the complementary-metal oxide semiconductor (CMOS) circuits generating arbitrary chaotic signals. Pulsewidth modulation approach suitable for very-large scale integration nonlinear dynamic systems; CMOS circuits for arbitrary chaos generation; Measurement results of a CMOS chip; Conclusions.