Search

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

The 40nm CMOS WLAN transceiver which support 802.11 a/b/g/n/ac dual band with integrated power amplifier is implemented. The transceiver covers 2.4GHz band and 5GHz band for 802. 11a/b/g/n/ac. The wireless transceiver includes RF Transceiver, power amplifier, LO generator and high speed data converter. To achieve better LO phase balance and lower power consumption, the harmonic VCO frequency is adopted and the power amplifier and the VCO were sufficiently isolated to prevent degradation of LO performance at high power. To compensate LO power attenuation, LC tuning is proposed. The transceiver is fabricated using 40nm CMOS process with 5.4mm2 die area. The power consumption of 802.11ac is about 160mW and 180mW for 2.4GHz receiver mode and transceiver mode except PA respectively and 170mW and 190mW for 5GHz case. The maximum PA output power 20.1dBm with 4.4% EVM without LO pulling. The 802.11 a/b/g/n/ac receiver noise figure is 2.7B and 3.3dB at 2.4∼2.5GHz band and 4.8∼5.7GHz band.

The 65nm CMOS wireless connectivity SoC which support 802.11 a/b/g/n, BT and NFC is implemented. The SoC cover 13.6MHz band for NFC, 2.4GHz and 5GHz band for BT and 802. 11a/b/g/n. The SoC includes RF Transceiver, Baseband modem for 802.11 a/b/g/n, BT and NFC and ARM9 core with various peripherals. The Soc is fabricated using 65nm CMOS process with 5.5 × 5.5 mm2 die area. The power consumption of 802.11n is about 160mW and 180mW for 2.4GHz receiver mode and transceiver mode except PA respectively and 170mW and 190mW for 5GHz case. The 802.11n maximum throughput is measured to 150Mbps. The 802.11 a/b/g/n receiver noise figure is about 4∼5dB at 2.4∼2.5GHz band and 4.8∼5.7GHz band. The sensitivity is about −88.7dBm at MCS0 mode. The sensitivity of BT is about −94dBm. NFC operation range is up to 3.5cm.

For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The mobile broadcasting markets are maturing rapidly for applications such as mobile cellular phones, car navigation, PMP and so on. The market drives low-cost, low-power and small size significantly for mobile applications and drives multiple functionality and multiple bands [1]. To meet the market requirements, more integration of system blocks and functionality is needed. To achieve this goal, the 65nm CMOS and multistandard and multiband receiver SoC may be suitable solution.

This paper provides a complex band-pass filter (BPF) for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner with I/Q gain and phase mismatch calibration. This calibration can be implemented in the first stage of complex BPF using feed-through resistor calibration scheme. The automatic tuning circuit with programmable clock is also presented. The measurement results show 1.536 MHz bandwidth with 2.048 MHz IF center frequency and 50 dB stop band attenuation at 0.7 MHz frequency offset. The in-band and out-band 3rd order intermodulation distortion (IMD3) are 55 and 60 dBc, respectively. After I/Q mismatch calibrating, 20 dB image rejection ratio (IRR) improvement is obtained from 38 dB to 58 dB in this work. The automatic tuning circuit guarantees less than +/- 4 % cut-off frequency variation covering the several clock requirements from demodulator ICs. The complex BPF is fabricated in 0.13 mum RF CMOS technology and consumes 9 mA with 1.2 V power supply.

A UHF mobile single chip RFID reader is implemented in 0.18 mum CMOS process. Developed IC achieves DA output power of 3 dBm, OIP3 of 14.8 dBm, phase noise of -100 dBc/Hz at 100 kHz offset, noise figure of 35.5 dB for talk mode, 6.2 dB for listen before talk (LBT) mode, and current consumption of 108 mA from a 1.8 V supply. With an external PA, Tx output generates output power of 27 dBm with OIP3 of 42.5 dBm. A leakage signal cancellation scheme is employed to suppress inevitable Tx leakage into Rx input. At a distance of 90 cm between antenna and tag the average recognition ratio is increased from 0% to 42.8% by the leakage canceller.

A low power high linear transmitter for mobile WiBro and WiMAX is developed. The transmitter is fabricated in a 0.18 mum 1P6M CMOS process for low power characteristics and SoC compatibility. To achieve high linearity performance with low power consumption, the transmitter employs new linearization methods. Linear transconductor is used for the transmitter mixer. The transconductor utilizes a negative feedback amplifier and a current mirror amplifier (CMA). In addition, a multiple-gated transistor (MGTR) with two auxiliary transistors and resistive source degeneration are used for the driver amplifier. With the proposed linearization techniques, a high linearity of 30.5 dBm OIP3 is achieved with 97.2 mW power consumption from a 1.8 V supply.

A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2nd-harmonic feedback effect caused by an inductive source degeneration. A 2.4-GHz differential driver amplifier has been implemented in 0.18 mum CMOS for Mobile WiMAX and Korean WiBro applications. It shows that the linear region with OIP3 of >+20dBm is extended up to an output power of -5 dBm, while achieving a maximum OIP3 of +28 dBm, OPldB of +7.8 dBm, and a power gain of 9.2 dB with dc power consumption of 1.8V and 18.7 mA.

A 0.18mum CMOS dual-band low-IF mobile-TV tuner IC for T-DMB/DAB that supports Band-III and L-band is presented. By modifying a few metals and via masks, the IC can support VHF and UHF bands for ISDB-T partial reception. The chip meets all the specifications of both applications with a sensitivity of

This paper provides a channel select low-pass filter with automatic cut-off frequency tuning circuit for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner IC. This filter has 1.58MHz cut-off frequency, 20dB and 65dB stop band attenuation at 1.9MHz and 2.4MHz, respectively. The in-band IIP3 is -8.4dBV and 1dB desensitization is satisfied for 490mVpp interferer at 1.7MHz frequency offset. By using simple automatic tuning technique, less than +/-1.5% cut-off frequency error and more than 40dB adjacent channel rejection (ACR) are obtained. The low-pass filter is fabricated in 0.18/spl mu/m CMOS technology and consumes about 4.5mA with 1.8V power supply.

The image rejection mixer for digital audio broadcasting and digital multimedia broadcasting (DAB/DMB) is described. The mixer is implemented in a 0.18mum six-layer metal CMOS process and occupies a 2.25mm2. To obtain the ultimate level of image rejection without additional tuning, the double quadrature architecture is used and to linearize the RF buffer, differential transconductance linearization technique is used (Tae wook Kim, et al., 2005). The fabricated mixer exhibits 65 dB image rejection ratio, 41dB adjacent channel rejection ratio, 100 kHz ~ 1.65MHz image rejection bandwidth, 16dB gain, 35dBmV input-referred third order intercept point (IIP3), and 15mA current consumption from 1.8V supply

A direct-conversion satellite tuner-demodulator IC is realized using 0.18/spl mu/m CMOS technology. The IC down-converts a 950-2150MHz satellite broadcasting signal to base band and demodulates the signal to an MPEG data stream. The IC conforms to both DVB-S and DSS standards. Experimental results show a 9dBm IIP3 while consuming 230mA from 1.8V supply.