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182 results on '"Martin, D. F."'

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1. GPU-accelerated Path-based Timing Analysis

2. An Efficient Work-Stealing Scheduler for Task Dependency Graph

3. An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints

5. An Efficient and Composable Parallel Task Programming Library

6. Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale.

7. Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs

8. Accelerate analytical placement with GPU: A generic approach

9. Routing at compile time

12. OpenTimer v2: A New Parallel Incremental Timing Analysis Engine.

13. High-Level Synthesis for side-channel defense

14. On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography.

19. Performance evaluation considering mask misalignment in multiple patterning decomposition

20. Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout

22. On fast timing closure: speeding up incremental path-based timing analysis with mapreduce

23. Contact pitch and location prediction for Directed Self-Assembly template verification

24. Polynomial time optimal algorithm for stencil row planning in e-beam lithography

27. DtCraft: A High-Performance Distributed Execution Engine at Scale.

28. Efficient simulation-based optimization of power grid with on-chip voltage regulator

29. CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design

33. The nature of optimization problem challenges in physical synthesis

34. Advances in wire routing

35. A novel and efficient method for power pad placement optimization

36. Network flow modeling for escape routing on staggered pin arrays

37. An ILP-based automatic bus planner for dense PCBs

38. Linear time algorithm to find all relocation positions for EUV defect mitigation

39. Algorithmic study on the routing reliability problem

40. Thermal via structural design in three-dimensional integrated circuits

41. Parallel implementation of R-trees on the GPU

42. Efficient pattern relocation for EUV blank defect mitigation

43. Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design

47. BDD-based circuit restructuring for reducing dynamic power

48. A negotiated congestion based router for simultaneous escape routing

49. Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid

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