Search

This paper presents a methodology of a basic analog blocks retargeting from bulk to fully depleted (FD) SOI technology. The design methodology is generally not related to the model used for the circuit simulations. However, the proposed one is closely linked to the EKV MOS model [1] that has been chosen for the FD SOI circuit simulations. Same of EKV parameters are used and expressions along with the g(m)/I-D design approach to demonstrate that the basic analog circuits are simply retargeted from bulk to SOL.

Growing demand for the solid state meters for power and energy measurement leads to the fully integrated Hall sensor based microsystem solutions. In this paper we describe fully integrated SOI Hall sensor based microsystem for power and energy measurements with dynamic offset cancellation. Since Hall sensor behaves like a natural four quadrant multiplier it is used to multiply the line voltage and current giving the output voltage proportional to the instantaneous power. Furthermore, voltage at the Hall output is proportional to the line active power and can be further processed. By converting the sensor output voltage to digital signal using a sigma-delta demodulator followed by digital filtering, the energy consumption is observed at the end of the processing chain. The entire microsystem has been designed for high linearity and resolution, and integrated in 0.5 /spl mu/m FD SOI process.

A new integrated architecture for power measurements is proposed. The system includes the Hall sensor bias circuit and its front-end voltage amplifier. The implemented architecture performs the conversion of the electrical power into a Hall voltage, which is then amplified by a Differential Difference Amplifier (DDA). The architecture shows low power consumption and an optimized area however its resolution is drastically limited by the sensor offset and the linearity of the DDA. In order to achieve higher resolution, a second system is also proposed where a dynamic offset cancellation is employed in the bias scheme in order to reduce both the sensor and the electronics offset. To improve the sensor amplifier stage, a linearized version of the DDA is used. The latter architecture appears to be very promising and a linearity of 16-bit is achieved. Both simulations and measurements results from the comparison between the two architectures are shown in this paper.