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This paper discusses the utilization of modular hardware devices in an educational context. As the leading platform for such purposes, we first describe the ingredients at the origin of Arduino's success. Examples of student projects and seminars based on this platform will illustrate how Arduino triggers innovation by providing an accessible programming interface and rich reusable content. Based on several experiences, we describe the design of a platform environment for smart wireless sensors reusing key concepts from Arduino to facilitate and accelerate development and deployment time. The usage of the new platform and design interface in student projects is described as well.

This works introduces a wireless signal processing platform based on a low-power FPGA. The architecture of the circuit is customized for the processing of sensor data used in biomedical applications such as ECG, EEG, or activity recognition using wearable computing. Hardware accelerators can be dynamically reconfigured to implement multiple signal processing tasks in a time-multiplexed manner. This approach allows reducing the size of the computing hardware while enabling energy-efficient operation. The functionality of the system is demonstrated for feature extractions in activity recognition applications.

A procedure to remotely control hardware reconfiguration at runtime is introduced in this paper. Low-level interactions are abstracted by a middleware service that can be called by requests issued by the user or by the underlying operating system. The dynamic loading of hardware modules is managed by a kernel reacting to user-defined events with a customizable scheduling strategy. The system has been designed in a flexible and portable way to support most common runtime reconfiguration approaches and operating systems. Interactions with the middleware are based on commands allowing custom composition and scheduling of hardware modules after deployment. The operation of the middleware is illustrated with the example of a remotely reconfigurable sensor node in a high-performance wireless sensor network.

We demonstrate an organic smart label electronic system using p-type organic thin film transistors (OTFT) for temperature sensing applications. The electronic label consists of all organic temperature sensor, memory, logic and interface circuits and detects whether the critical temperature threshold value has been exceeded and records the data digitally in write-once-read-many (WORM) form that can be transmitted to a reader through wireless communication. A comparator is used to interface the sensor to the logic part. The logic circuit block processes and bundles the sensor information along with the necessary additional information that is required for a successful wireless transmission. We have demonstrated the operation of the reported organic smart label system using a silicon based modulator/rectifier circuit for RF communication. The organic logic circuit was built using standard cell design approach with approximately 180 p-type OTFTs. All the circuits were operated with a VDD of -20 V.

This paper presents a technique for correcting the spectral leakage which occurs in windowed time series. The presented technique is aimed to be implemented on an autonomous embedded device based on reconfigurable hardware. This device is intended for being used in remote condition monitoring of motors. As a matter of example, the technique is used to analyse the common frequency components appearing in faulty motors suffering from inter-turn short circuits.

Summary form only given. Smart or intelligent system is a new technology term that will be found in many applications in our daily life and industries in the future for examples in energy management, medical applications and healthcare management, industrial automation and automotive. Based on its technological term, smart systems should have capabilities to solve very complex problems, including taking over human cognitive functions. Due to the exponential increase of world energy demand, in which between 2010 and 2030 is estimated to be 45%, energy management will be one of the most urgent topics of the century and a significant driver for the evolution of semiconductors and electronics products. The important issues in the energy management are efficiency and reliability. Those requirements initiate the movement of power technology trend from traditional into smart grids concept. Cybersecurity and control systems for instance will be important topics for future smart grid systems. In medical applications and healthcare management, smart products are mainly dedicated to improve the quality of health treatments and rehabilitations. The key components of the products are sensors (biomedical sensors). They should be miniaturized, which is enabled by using Micro-Electro-Mechanical System (MEMS) technology, in order to minimize the physical effect on the biologic system. The key factor of the smart systems is new inventions in the fields of nanotechnology, advanced materials, biotechnology, photonic technology and nanoelectronics. The innovation of efficient computing algorithms should be a challenging issue to implement the nanoelectronic products. The integration of the nanoelectronic products into smart systems should consider both arts and cost aspect. Therefore, the miniaturization of smart products, which is affected by efficient computing algorithms and nano-scale technologies, will be an interesting feature for end-users on market.

Dynamic mapping heuristics can cope with dynamic application scenarios by allocating tasks to cores of an MPSoC during runtime. In this paper, we compare eight heuristics in terms of the response time of application tasks - that is, the time between the issuing of a task and the time when it completes executing and communicating. By taking into account the task execution, communication and waiting times, we could better evaluate the quality of the different heuristics and show that there is room for improvement when it comes to heterogeneous platforms under high utilization.

This paper presents a solution for the low-cost implementation of diagnosis techniques for induction motors using networked intelligent wireless sensors. Based on computation “at the edge”, the proposed approach is particularly suitable for large networks. The analysis of the stator current spectrum of a broken rotor bar is presented as study case. The suitability and the implementation efficiency of the Zoom-FFT algorithm on the smart wireless sensor based on reconfigurable hardware is demonstrated.

Due to the cost-effective nature and deployment flexibility of wireless sensor network (WSN), it has been extensively used in many real world applications. Sensor nodes are relatively inexpensive and capable of data processing and wireless communication with some level of intelligence, they play a key role in real world applications. Precision irrigation in agriculture is a key application of wireless sensor network. Typically, a sensor node is powered by its on-board battery source. This limitation fully or partially contributes to causing many problems in the network such as the loss of connectivity of a sensor node known as orphaned-node. Moreover, available number of sensor types in a sensor node is typically limited and it requires a significant modification in hardware and software interfaces to extend the number of sensor types. In this paper, we propose an adaptive sensor node system combining a flexible hardware prototype and innovative energy harvesting techniques to optimise the performance of the network operating in a large farming environment.

An intuitive tool for the elaboration of configuration data for a Coarse-Grained Dynamically Reconfigurable Architecture (CGDRA) is presented in this paper. A Graphical User Interface (GUI) allows developers who are not familiar with the design or with dynamic reconfiguration, a quick elaboration of an algorithm implementation with the help of function blocksets. The generated configuration data is then uploadable in the core at runtime and can be remotely activated in order to execute the desired functionality. The interface also allows a rapid selection and arrangement of the elements composing the smart sensor interface and an adaptation of the design to a large range of applications. The system architecture is particularly suitable for resource-constrained embedded systems like Wireless Sensor Networks (WSNs) where it can be used for energy and time-efficient data processing or on-demand hardware acceleration.

This paper presents an historical review of the establishment of an academic programme introducing teaching and research on FPGA-based system design in the Mongolian High Education. The main strategy was to found a Microelectronics research group within several departments of the Mongolian University of Science and Technology (MUST) and promote the education of microelectronics design not only at the MUST, but also throughout Mongolia. The education process adopted at the Computer Science and Management School (CSMS) of MUST will be presented. Under the Microelectronics group initiative, a set of events (Electronics Olympiad, seminaries and workshops) was set up in collaboration with other Mongolian Universities as an important action for the dissemination of FPGA-based system design. The presence of students and faculty members in international activities had also an important effect. Results of research and teaching practices will also be presented.

Encryption and channel coding are both essential steps for reliable, robust and secure operation within wireless networks. Usually, these algorithms are considered independently of each other because of their antagonism, but solutions exist to combine their features into a single simple primitive. This fusion aims to improve the performance and the energy-efficiency of the wireless device while contributing to the dependability of the whole system. The introduction of a dedicated core implemented on field-programmable logic tightly coupled to the central controller of a wireless sensor node demonstrates further benefits for the energy-efficiency of the system.

Design and evaluation of a CORDIC (COordinate Rotation DIgital Computer) algorithm for a floating-point division operation is presented in this paper. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. A hardware architecture of CORDIC algorithm capable of processing broader input ranges is implemented and presented in this paper by using a pre-processing and a post-processing stage. The performance as well as the calculation error statistics over exhaustive sets of input tests are evaluated. The results show that the CORDIC algorithm can be well-convergence and gives precise division operation results with broader input ranges. The proposed hardware architecture is modeled in VHDL and synthesized on a CMOS standard-cell technology and a FPGA device, resulting 1 GFlops on the CMOS and 210.812 MFlops on the FPGA device.

To improve the computation precision of the beams control system in a heavy ion accelerator system, a floating-point phase and magnitude digital detector is proposed. The coordinate rotation digital computer (CORDIC) algorithm is utilized to compute results in digital form. Due to the hardware design simplicity, shifting and adding operations become two main operators to perform the computation. The proposed CORDIC core is based on floating-point arithmetic units to obtain high accuracy for the closed-loop control system. A Pipeline-based architecture is applied instead of CORIDC's iteration process in order to maximize computation performance. Moreover, comparison of hardware 8-and 16-stage pipeline-based simulations with Matlab/simulink is statically analysis to differentiate the accuracy of the two hardware architectures. Finally, resource efficiencies based on target Xilinx FPGA xc5vlx110 and 130-nm Silicon technology are shown that 8-and 16-stage hardwares consume maximum 18% and 38% of total slices at 134 MHz on the target FPGA, as well as 43,164 um and 83,769 um at 617 MHz on Silicon technology.

A dynamically reconfigurable architecture tailored for low power wireless sensor networks is introduced in this work. Using resource sharing and frequent reconfiguration, the power consumption of the hardware is kept low while data processing is still efficient. Remote reconfiguration becomes also possible with very low overhead.

A reconfigurable and programmable streaming processor core complemented with interconnected arithmetic units for the acceleration of floating-point operations is presented in this paper. The streaming processor can be easily reconfigured to perform a complex scientific algorithm or computations by changing the set of instructions in a central control unit. By using floating-point arithmetic unit with pipeline streaming data flow, floating-point operations can be performed in each cycle resulting in a high-performance scientific computations. The streaming processor is dedicated for a high-performance adaptive signal processing applications. For higher performance, reliability and fault-tolerance scientific computations, the streaming processor would be designed as a tile processor in a multicore streaming processor system.

The rapid improvement of semiconductor technologies is the enabling factor for the design of large-scale System-on-Chip (SoC) architectures. At the same time the scale-down of feature sizes in silicon technologies brings up new challenges as parameter variations of the transistor devices, an increased vulnerability for wear-out effects during the lifetime of the device and increased sensitivity for soft-errors. The overall system reliability is therefore an important topic to be addressed in the SoC design process as well as economic considerations related to manufacturing yield and lifetime maintainability. The aim of this contribution is to outline implications for the design process and to illustrate the dependability aspects at the example of SoC communication architectures being implemented as Networks-on-Chip (NoCs).

A platform for the prototyping of distributed sensing and actuating applications is presented in this paper. By combining a low power FPGA and a System-on-Chip specialized in low power wireless communication, we enabled the development of a large range of smart wireless networks and control systems. Thanks to multiple customization possibilities, the platform can be adapted to specific applications while providing high performance and consuming little energy. We present our approach to design the platform and two application examples showing how it was used in practice in the frame of a research project for adaptronics.

This paper presents an implementation of a radio frequency wave energy harvester with the capability of self-adjusting the matching network to adapt to changing load conditions. An auxiliary charge-pump is designed to supply the power for the supplemental control unit. The design is implemented in a standard 0.13-µm CMOS process. The results show that the power transfer efficiency with using the proposed design can achieve a level of over 70% independent of the load conditions.

An architecture for a dynamically reconfigurable co processing unit for a wireless sensor node is presented in this paper. The hardware accelerator is tailored for the processing of sensor data streams that cannot be efficiently handled by low-power micro controllers. High energy-efficiency is obtained by using reconfigurable computing mechanisms. The details of the architecture including multiple, specialized, reconfigurable processing stages are introduced. For a fast and efficient dynamic reconfiguration, the size of the reconfiguration data is minimized by using multiple reconfiguration levels. Reconfigurable function units are reused for the implementation of different algorithms sharing arithmetical properties. Thus, only a few resources are required for reconfiguration, limiting the power consumption of the node while its computation performance is increased with application-specific accelerators. An application example illustrates the utilization of the processing unit for the acquisition of accelerometer data.

A concept for reconfigurable communication infrastructure for networked control systems is presented in this paper. The communication infrastructure consists of two communication protocols, i.e. wireless communication and wired communication protocols. The concept is dedicated for a hard real-time distributed parameter control system, where each local control module is implemented as a platform with multiple/interconnected reconfigurable and programmable devices such as Field-programmable Gate Arrays (FPGAs) and microcontrollers. Adaptive networked multiprocessing algorithms can be further mapped onto the platform for specific real-time control applications. Data exchanges between multiple control units on a hardware platform are controlled by multicast-enabled switches that are also implemented on the FPGA devices. Data exchanges between platforms in a more complex system are controlled by a wireless standard communication protocol. The exchanged data can be sensor signals, actuating signals and system parameters. A bit-level parallel handshaking interface (PHI) adapter is introduced to handle the inter-switch data communication between the FPGA devices.

A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.

One problem of Multiprocessor Systems-on-Chip (MPSoCs) based on Networks-on-Chip (NoCs) is tracing the dozens of parallel communications that are transferred in the system. The goals of tracing communications are usually either debugging or monitoring the NoC for design space exploration. On Register Transfer Level (RTL) NoCs the tracing is frequently verified by waveforms, which provides limited useful information about the global status of the NoC. The goal of this work is to improve the tracing capabilities of RTL NoCs and provide a global picture of what is happening in the NoC. This is accomplished by using a Java tool to represent graphically relevant events of the NoC. The input of this tool is a list of relevant events generated by the RTL simulator during the simulation of an MPSoC. The HERMES NoC is used as test case for the tool.

Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.

The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

Many papers reporting microelectronic chaos based applications have appeared in recent years. The focus of cryptology has been mainly on the algorithm implementation rather than on the chaotic system choice. In this paper, a novel method is proposed which aims at properly selecting a chaotic system to be used with encryption algorithms. The properties directly related to the algorithm strength and implementation complexity are the parameters that guide the system choice. Six chaotic systems have been examined with a summary of the data for quick design application made available.

This paper presents the first synthesizable network-on-chip (NoC) based on a mesh topology, which supports adaptive and deadlock-free tree-based multicast routing without virtual channels. The deadlock-free routing algorithms for unicast and multicast packets are the same. Therefore, the routing function gate-level implementation is very efficient. Multicast packets are injected to the network by sending multiple packet headers beforehand. The packet headers contain destination addresses to set up multicast trees connecting a source with multiple destination nodes. An additional locally uniform identification (ID) field is packetized together with flits belonging to the same packet. Therefore, flits of different unicast or multicast packets can be interleaved in the same queue because of the local ID-tags, which are updated and mapped dynamically to support bandwidth scalability of interconnection links. Deadlocks in tree-based multicast routing are handled using a flit-by-flit round arbitration and a fair hold???release tagging mechanism. The effectiveness of the novel mechanism has been experimented under multiple multicast conflicts scenarios, where the experimental results show that all traffic is accepted in-order and lossless in their destination nodes even if adaptive routing functions are used and the sizes of the multicast messages are very long.

As the number of cores increase in a single chip, Networks-on-Chip (NoCs) are more and more the chosen solution to communicate intra chip cores. Most of the NoCs so far have been successfully implemented on hardware description languages and its debugability based on waveforms. For really exploring and monitoring NoCs, a more high level abstraction description of the NoC and a more user friendly interface is required and presented in this work. New algorithms and ideas can be created for the NoC and executed together with the target application. Besides the usual text or visual outputs that the application may have, embedded software developers may take advantage of the following monitors to know what is happening on each port of each router of the NoC: input traffic, output traffic, hot spot information, power consumption, buffer occupation, end to end and point to point connections. One application is presented and two different improved mappings are presented based on the information given by the monitors.

A novel multi-protocol RFID reader with automatic power control is proposed in this paper based on a software defined radio architecture. The transponder power consumption variation over time is considered for different protocols. The modulation effect of power control on forward data transmission is included in the analysis. The emission power of the reader is automatically tuned in real-time according to the needs of the transponders in compliance with different standards, with which a considerable amount of power can be saved.

Image and video processing is indispensable for modern traffic surveillance applications. At this, the reliable detection of vehicles is an essential and also challenging task depending on versatile environment parameters. Many research works have been investigated in accurate pattern matching so far. Nevertheless, dealing with noise and variations in pattern shapes are still improvable key problems. This paper presents a novel approach enabling robust detection of vehicles in static frames. The proposed algorithm extends the classical distance transform approach and provides vehicle-specific clutter depression methodologies. In this regard, experimental results are given on diverse traffic scenarios.

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20°C. Within the range 20 – 60°C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

We explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which combines high energy efficiency with programmability and hence meets the requirements of small energy-constraint embedded systems. Its energy consumption, area, and performance are evaluated and compared to processor and ASIC architectures. Our case study particularly focuses on the question if the architecture concept of frequent dynamic reconfiguration of a small heterogeneous data path can lead to suitable system solutions for the target domain. To answer this, the effect of the reconfiguration overhead on total system efficiency is examined closely. As important result, our experiments show the low energy consumption achieved, the low reconfiguration overhead, and the specific region of the architecture in the design space between processors and ASICs. In particular, large energy-savings of factor 2 to 6 and speed-ups of factor 6 to 14 compared to processors are obtained on average. Our work shows the high suitability of frequent runtime reconfiguration of small coarse-grain data paths for the design of very efficient but yet programmable embedded systems platforms.

Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control on the FPGA. First, we extend our existing tool flow with a novel mechanism for efficient partial multi-context reconfiguration and provide tool support to generate according circuitry, control, and configuration data. Second, we propose an extension of current FPGA architectures to efficiently support cycle-based runtime control. We employ a special contentaddressable multi-context memory resource for controlling the datapath functionality, which on average requires only 15% memory for storing the control data compared to a BlockRAM based approach, and only 53% compared to regular multi-context switching.

This paper presents the necessity and potential of using tunable matching network in UHF RFID transponders. A compact I/V model for diode-connected MOSFET in strong inversion and sub-threshold regions, which is based on the UMC 0.13-µm technology, is utilized to analyze the influence of the dynamic load to the performance of the power harvesting circuit. A direct dependence of the voltage sensitivity on the varying load current has been found and formulated. The dependence suggests the necessity of optimizing dynamically the impedance matching network between the antenna and the rectifier according to the transponder operation status. A concept of the operationcontrolled tunable matching network is finally proposed.

Synthetic Floating-Point (SFP), a synthetic benchmark generator program for floating-point circuits is presented. SFP consists of two independent modules for characterisation and generation. The characterisation module extracts key dataflow statistics of an arbitrary software program. Generation involves producing randomised circuits with desired statistics which are either the output of the characterisation module or directly generated by the user. Using the basic linear algebra subprograms (BLAS) library, Whetstone benchmark and LINPACK benchmark, it is demonstrated that SFP can be used to generate floating-point benchmarks with different user-specified properties as well as benchmarks that mimic real computational programs.

Hardware reconfiguration during run-time provides attractive features like fast adaptivity, high hardware utilisation, and low area consumption due to efficient reuse of hardware components. In this paper, a novel multi-layered reconfiguration mechanism is proposed that allows frequent dynamic reconfiguration at very low latencies. It combines successful existing techniques such as multi-context and partial reconfiguration with new ideas like tag-matching and reconfiguration profiles to one uniform approach. As an important feature, the proposed reconfiguration mechanism is well scalable and can be adapted to given hardware structures easily, thus being applicable to virtually any reconfigurable fabric. In contrast to many existing techniques, it also supports even very heterogeneous architectures found for instance in custom reconfigurable systems. By experimental results, we show that our reconfiguration mechanism provides significantly lower reconfiguration latencies compared to some common existing techniques.

We present a hardware implementation of an efficient image compression method optimised for small FPGAs. The compression method is based on a codebook of reference patterns to support multiplication-free quantisation of the image data. Based on specific features of a low-cost FPGA architecture, a pipelined implementation is developed and evaluated. The implemented hardware benefits from the simple structure of the compression method and is optimised for area and performance. The realised hardware as well as the underlying compression mechanism are described and the synthesis results for different model variants are compared. The results show that a high compression rate is possible at extremely low hardware costs. Also, a high frame rate can be obtained even on a low-cost FPGA.

High-speed bandpass DeltaSigma modulation is desired in applications that require analog-to-digital conversion of narrowband signals centered around intermediate frequencies. Two different approaches exist to implement the resonators needed by a switched-capacitor (SC) bandpass modulator. Both methods use a negative feedback loop around two elements. In the first approach, these elements are SC integrators, and, in the other approach, they are implemented with SC delay cells. In this paper, the impact of nonideal circuit behavior on the center frequency and quality factor of these resonators is analyzed and simulated when used at fs/n. The nonidealities considered are finite operational amplifier gain, finite unity-gain bandwidth, and nonzero input capacitance.

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs). Our architecture is based on processing elements which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, IEEE 754 floating-point arithmetics are used to compute the transformation. We also consider the normalization step which takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 8 processing elements and 2 times 256 words memory in a 0.18-mum technology is 2.2 mm2 and the estimated operating frequency is 340 MHz.

FPGA implementations of complex image processing algorithms are often limited in flexibility and by the amount of available chip resources. This article presents a hardware design of an adaptive self-reconfigurable video processing platform. Dynamic self-reconfiguration increases a designpsilas flexibility and enables the use of FPGAs with a fraction of resources actually needed by the algorithm. As a case study two implementation approaches of a complex frame-grabber with a set of dynamically reconfigurable kernels are evaluated and further improvements are outlined.

High level system modeling has significant impact on the early analysis and evaluation of the embedded electronic systems. Being a class of distributed embedded systems, wireless ad hoc sensor networks can benefit from such system-level modeling, but require a suitable mobility model in order to analyze and design reliable and energy-efficient communication protocols. In this paper we propose an actor-oriented group mobility model for wireless ad hoc sensor networks dedicated to wildlife tracking and monitoring. The model can present individual and group motion according to the specified movement patterns, which in turn are characterized by the average moved distance and the average turning angle.

Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.

In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a re-configurable sensor node prototype platform, and an auxiliary network structure for granting a reliable communication channel for runtime debugging without interfering with the primary radio link. For the prototype platform, we propose a modular design which incorporates a single FPGA with high gate count as core of the platform. The FPGA is utilized to emulate arbitrary mote architectures and realize flexible interfaces to sensors and radio transceivers. As a major benefit, versatile debugging interfaces can additionally be implemented in the same FPGA, seamlessly integrating into the emulated mote architecture, with direct access to internal information. This easily allows to realize passive system monitors as well as active debugging control. By using a deployment support network to exchange relevant information, all motes can be monitored and controlled simultaneously by a user. The paper presents the proposed methodology, its implementation, and a practical application example in detail.

Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation of both device reliability and system performance. As the process technology is scaled down, the effects of process variation are becoming significant on system performance. In order to incorporate the combined effects process variations on the performance of on-chip bus architecture, this work proposes a technique to synthesize an energy conscious robust on- chip bus architecture. The proposed model simultaneously performs on- chip bus synthesis and voltage scaling under both data size and process parameters variations. The problem is relaxed to a nonlinear optimization model, which synthesizes an energy conscious optimal bus widths and the number of buses considering worst case data traffic and process variations. The experimental results show that applying voltage scaling during the synthesis of on-chip bus effectively reduces the dynamic power consumption, leakage power consumption, and mitigates the effects of process variations.

This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity mapping management. The NoCs are developed based on VHDL-modular approach to support the design flexibility. The on-chip router switches packets using wormhole packet switching method with synchronous parallel pipeline technique. Contention-free routing algorithms and dynamic packet identity management are proposed to support wire- through-share methodology and identity-slot division multiple access technique. The on-chip routers are also equipped with packet flow control and automatic injection rate control mechanism to avoid packet-loss, when the NoC is congested. Some static and adaptive routing algorithms are implemented in the NoC to observe the performance of the NoC over some selected network traffic patterns and the logic consumption (using CMOS standard-cell library). Area overheads to implement several adaptive routings over static routing algorithm are less than 9%. Our NoC guarantees in-order and lossless message flits delivery.

In this paper, a new concept for a very flexible and modular prototype platform for rapid prototyping of wireless sensor networks is presented. We propose to use a FPGA with high gate count as core of the platform. The FPGA is utilized to attain 3 major goals for the prototype platform: to emulate arbitrary mote architectures even including smart motes with high system complexity, to realize flexible interfaces to sensors and radio transceivers, and to embed versatile debugging and system monitoring functionality in the mote prototypes. The presented prototype platform is suitable to realize complete sensor networks based on different mote architectures, different wireless communication schemes, and arbitrary application domains. The design concepts and implementation aspects of the platform are presented and discussed in detail.

Application-specific reconfigurable processor architectures provide a remarkable potential for systems which achieve concurrently high performance, area efficiency, energy efficiency, run-time adaptivity, and sufficient flexibility. Thus, they represent competitive design alternatives that provide significant improvements in some of these figures of merit in comparison to non-reconfigurable architectures. Research results of three projects on the analysis of architecture concepts, design, and evaluation of application-specific reconfigurable processors in different domains are presented.

In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and power cost, performance, and reconfiguration time. Thus, architectures with coarse-grained reconfiguration features have also been studied in projects (Sec. 1, 2, 4) within the priority program Reconfigurable Computing Systems and the project CoMap (Sec. 3), which are all sponsored by the German science foundation.

In this paper, a new generic sensor node platform for wireless sensor networks (WSN) is presented, demonstrating that high energy efficiency, flexibility and performance can be achieved by the use of dynamically reconfigurable hardware in the WSN domain. The core of the presented platform is formed by the combination of a RISC processor and a dynamically reconfigurable function unit optimized for efficient data processing in WSN applications. A novel reconfiguration mechanism is applied enabling rapid dynamic reconfiguration with very short latencies. Thereby, we can show that the overhead on performance and energy consumption caused by dynamic reconfiguration can be reduced to a moderate, non-critical value and is clearly outweighed by the significantly improved performance and energy consumption for data processing on the reconfigurable function unit. The evaluation of the platform and its comparison to a standard processor-based platform finally demonstrate high gains in energy-efficiency of one to two orders of magnitude.

This work investigates the reduction of power consumption in networks-on-chip (NoCs) through the reduction of transition activity using data coding schemes developed for bus-based systems and proposes a new coding scheme suitable for NoC-based systems. The estimation of the NoC power consumption was performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels were embedded in a system model and a series of simulations were performed, aiming to analyze the trade-off between the power savings due to coding techniques versus the power consumption overhead due to the encoding and decoding modules. The proposed coding scheme presented the best results for all of the simulated traffic patterns, when compared to other coding schemes found in the literature.