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Emergency alert systems (EASs) have been deployed in some countries in order to broadcast emergency alerts and warning messages to the public. In this letter, we describe an innovative electronic embedded solution, named Firetec switch, intended to be placed in the FM radio stations. This switch will be supported by a server placed at the authorized officials, with the capability to generate the audio alerting messages. One interesting challenge is to deliver the messages only to the local public, in the catastrophe neighborhood, by using FM radio stations. This letter focuses on the description of the Firetec switch hardware and software. [ABSTRACT FROM AUTHOR]

Human activity recognition (HAR) is one of the most interesting application for machine learning models running on low-cost and low-power devices, such as microcontrollers (MCUs). As a matter of fact, MCUs are often dedicated to performing inference on their own acquired data, and any form of model training and update is delegated to external resources. We consider this mainstream paradigm a severe limitation, especially when privacy concerns prevent data sharing, thus model personalization, which is universally recognized as beneficial in HAR. In this letter, we present our HAR solution where MCUs can directly fine-tune a deep learning model using locally acquired data. In particular, we enable training functionalities for 1-D convolutional neural networks (CNNs) on STM32 microcontrollers and provide a software tool to estimate the memory and computational resources required to accomplish model personalization. [ABSTRACT FROM AUTHOR]

This paper presents a design paradigm to implement convolutional neural networks (CNNs) on low-power commercial microcontrollers for the detection of landing pads in small-size drone applications. A neural architecture search (NAS) strategy generates and selects CNN architectures automatically; candidate networks are compared in terms of their computing costs and representation capabilities. The proposed NAS procedure adopts a teacher-student learning paradigm, in which the ‘student’ network should mimic the ‘teacher’s’ intermediate representation. The associate selection strategy aims to attain an efficient feature representation that can take into account the peculiarities of the problem at hand. This approach allowed the generation of tiny networks capable of real-time execution on commercial micro-controllers (STM32 family). Experimental results confirmed that the resulting architectures could trade off generalization capabilities and computing costs effectively, and outperformed state-of-the-art solutions for landing-pad detection in small-size drones.

Motivated by the critical need for securing bio-signal transmissions in resource-constrained Internet of Medical Things (IoMT) devices, this paper proposes a novel lightweight cryptosystem based on a newly developed chaotic map called the Logistic-Coupled Memristor (LCM) map. This map is designed by coupling a discrete memristor with the well-known chaotic logistic map. The LCM exhibits a high degree of sensitivity to even slight changes in its ten control parameters, a crucial property for secure communication. We validate the chaotic behavior of the LCM using various established methods (Lyapunov exponents, bifurcation diagrams, parameter sensitivity analysis, and NIST randomness tests). Furthermore, we demonstrate its implementation on a low-cost microcontroller with limited resources. Building upon the LCM’s properties, we propose a novel lightweight cryptosystem for securing the wireless transmission of bio-signals. This cryptosystem is also implemented on a low-cost embedded system, showcasing its potential for real-world applications. Extensive simulations and comparisons confirm that the LCM map retains its chaotic behavior even when implemented on resource-constrained microcontrollers. Additionally, the implemented cryptosystem achieves a high level of security with lower cost in comparison to existing solutions.

We present the design, implementation, and results of an algorithm for respiratory rate (RR) estimation using respiratory-induced frequency, intensity, and amplitude variation calculated from the infrared (IR) channel of the SEN-15219 board for photoplethysmography (PPG) acquisition. First, the algorithm was developed in Python (on a PC) using synthetic signals and publicly available respiration and PPG data. We also include a graphical user interface to process data from sensors and display vital signs. Later, we ported the algorithm to an MSP432P401R microcontroller to complete our wearable prototype. Results are promissory and show that RR estimation can be performed on the selected platform with our proposed Fourier Product (FP) method, which results in a Mean Absolute Error of 4.1 using 16-s windows of IR-PPG signals. [ABSTRACT FROM AUTHOR]

Typical training procedures involve read and write operations for weight updates during backpropagation. However, on-device training on microcontroller units (MCUs) presents two challenges. First, the on-chip SRAM has insufficient capacity to store the weight. Second, the large flash memory, which has a constraint on write access, becomes necessary to accommodate the network for on-device training on MCUs. To tackle these memory constraints, we propose a partial weight update technique based on gradient delta computation. The weights are stored in flash memory, and a part of the weight to be updated is selectively copied to the SRAM from the flash memory. We implemented this approach for training a fully connected network on an on-device MNIST digit classification task using only 20-kB SRAM and 1912-kB flash memory on an MCU. The proposed technique achieves reasonable accuracy with only 18.52% partial weight updates, which is comparable to state-of-the-art results. Furthermore, we achieved a reduction of up to 46.9% in the area-power-delay product compared to a commercially available high-performance MCU capable of embedding the entire model parameter, taking into account the area scale factor. [ABSTRACT FROM AUTHOR]

Deep neural networks are currently applied in multiple domains, especially in the automotive industry. The main reason for this is related to the more complex challenges found in the field of signal processing, especially when the tasks involve image and video data types. Using conventional/statistical algorithms to deal with these high-complexity challenges is no longer a viable approach. Therefore, the involvement of artificial intelligence solutions like deep neural networks has significantly increased. In recent years, numerous architectures have been developed with the aim of maximizing performance. However, their size and computation requirements have increased at the same time. For this reason, special attention is currently being paid to the optimization of deep neural networks while trying to maintain (almost) the same performance. In this work, we aim to tackle the problem of eye gaze estimation considered within the automotive framework. Our proposal uses a knowledge distillation concept applied to a custom CNN architecture, called the teacher model. Based on this, several CNN student models are derived using layerwise and widthwise compression techniques. Furthermore, they are evaluated with respect to certain performance metrics, e.g. neural network size and inference time. In the experimental results, we propose certain compression methods which can address specific user requirements like model size, accuracy, and inference time. Finally, the student models are evaluated using an EdgeAI embedded device (STM32H747I-DISCO) in terms of accuracy, memory utilization, MACC complexity, and inference time. The combination of layerwise and widthwise compression results as the optimal method to derive student models with a good trade-off between the above-mentioned metrics. Using knowledge distillation, the accuracy can be improved by up to 9.5% over the conventional training procedure.

We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – $332~\mu \text{W}$ ) for the digital signal processing of the software-defined radios.

Monitoring sheep activity can be crucial for improving productivity and animal welfare. This work presents the design, manufacture, and test of a collar-type device to monitor sheep behavior. The device consists of an MSP-EXP432P401R microcontroller from Texas Instruments, a Bosch Sensortec’s BMI160 3-axis accelerometer, and a narrowband-IoT BG96 modem from Quectel that includes a global positioning system. The device has two operating modes: 1) validation mode (VM) to test and validate algorithms for characterizing sheep activity and 2) research mode (RM) to support multiday animal experiments to study their behavior. In VM, it sends accelerometer data, the animal’s state (run, walk, stand, or head down), and the location to the Central System every 20 s. VM has an autonomy of 51 h. In RM, the device transmits the animal’s state and the location every 2 or more minutes to extend the autonomy to more than ten days. The microcontroller identifies the sheep’s states (every 5 s) using real-time accelerometer data processed with an algorithm based on the linear discriminant analysis method. We trained a classifier on a PC using a public dataset, and then we ported it to the microcontroller. Preliminary tests show that the sheep’s state identification has a prediction success rate of 88%, opening exciting possibilities for developing an applicable device. [ABSTRACT FROM AUTHOR]

This document describes the design and implementation sequence of hardware and firmware components of two microcontroller boards of 8-bit and 32-bit architectures, which use similar form factors and share common input/output devices and recently developed Web-based user interfaces. These developments are the result of over two decades of experimentation in educational and research measurement systems in renewable energy projects. The boards are intended to fill a gap between low-cost hobby systems and high-end research loggers, especially where international standards require control of uncertainties, as is the case with small wind turbine power curve assessments. The focus was to increase reliability in the hardware aspects and make software development easier by including user-friendly firmware and a set of in-house C language coding rules for new developments and refactoring of legacy code. Testing of the low-level driver sections and the use of automated tools such as Ceedling for higher-level module testing are also described. [ABSTRACT FROM AUTHOR]

This article proposes a novel control for the multiple-input, single-inductor, multiple-output dc–dc converters. It is digitally and discretely implemented, which can have an outstanding performance in low-power applications so that at the power of 10 mW, it has an efficiency of 92.5%. Conventionally, in this power range, an attempt is made to take advantage of an analog design that is flexible. Thus, a fully programmable (software designed) converter with digital design using a microcontroller is in great demand. This converter design basis is to deploy the microcontroller's central processing unit (CPU) as little as possible. Also, it only turns on the CPU when necessary to be employed in low-power, portable systems, e.g., energy-harvesting technologies. Therefore, construction costs are significantly reduced. Depending on the energy level of the inputs, they can simultaneously be utilized to charge the outputs. This article uses stability analysis, time-multiplexing control method, and variable-frequency pulsewidth modulation in the proposed control design. Each output can be charged with different frequencies according to its load, and the maximum switching frequency is equal to 10 kHz. Also, the proposed technique for zero-current switching has been digitally implemented; it can be utilized to determine the optimal value of the inductor discharge duty cycle based on the inductor's left-side voltage. Comparative simulations and experimental results reveal the superiority and practicality of the proposed approach. [ABSTRACT FROM AUTHOR]

Blockchain creates a secure environment on top of strict cryptographic assumptions and rigorous security proofs. It permits on-chain interactions to achieve trustworthy properties such as traceability, transparency, and accountability. However, current blockchain trustworthiness is only confined to on-chain, creating a “trust gap” to the physical, off-chain environment. This is due to the lack of a scheme that can truthfully reflect the physical world in a real-time and consistent manner. Such an absence hinders further blockchain applications in the physical world, especially for the security-sensitive ones. In this paper, we propose a framework to extend blockchain trust from on-chain to off-chain, and take trustworthy vaccine tracing as an example scheme. Our scheme consists of 1) a Trusted Execution Environment (TEE)-enabled trusted environment monitoring system built with the Arm Cortex-M33 microcontroller that continuously senses the inside of a vaccine box through trusted sensors and generates anti-forgery data; and 2) a consistency protocol to upload the environment status data from the TEE system to blockchain in a truthful, real-time consistent, continuous and fault-tolerant fashion. Our security analysis indicates that no adversary can tamper with the vaccine in any way without being captured. We carry out an experiment to record the internal status of a vaccine shipping box during transportation, and the results indicate that the proposed system incurs an average latency of 84 ms in local sensing and processing followed by an average latency of 130 ms to have the sensed data transmitted to and been available in the blockchain. [ABSTRACT FROM AUTHOR]

Designing single-board computers (SBCs) is becoming more challenging given the growing number of discrete components that are made available and the rate at which this number grows. Keeping track of all available components options, revisions, and functionalities is challenging for SBC designers who are striving for faster design cycles. Moreover, the procedure of deciding peripheral components, their values, and connections of an SBC is not only difficult because of various parameters that need to be considered but also is time consuming as there exist numerous components on a typical SBC nowadays. In this article, an SBC generator tool, FASCINET, is presented that uses a neural network (NN) model to design customized peripheral circuits for SBCs. The tool creates a large commercial off-the-shelf database (COTS DB) of existing components, efficiently searches through them, and selects optimal components for both main and peripheral components based on the user’s requirements. Creating such a broad COTS DB requires processing abundant datasheets. A manual approach is time consuming, even if only a fraction of all available datasheets is considered. In order to automate this process, this article describes a novel NN-based approach for automatically categorizing datasheets and proposes an extraction technique for parsing relevant functional information from tables within. Our evaluation using a test set that contains over 770 000 components shows that the category of datasheets is identified correctly over 95% of the time. Additionally, the table extractor has a precision above 96%. Our proposed fully autonomous SBC design approach reduces the time for generating the schematic of an SBC to as little as 2 min. For validating the accuracy of our model, the netlists of 400 SBCs designed by FASCINET are compared to the human-designed versions. This evaluation shows that FASCINET is able to design SBCs that are identical to the manually designed ones except for minor differences. [ABSTRACT FROM AUTHOR]

Large-scale deployment of low-power sensing and computing units calls for unique power management solutions to overcome the inconvenience, costs, and waste problems associated with batteries. Energy harvesting offers an exciting solution to the battery problem, enabling circuits that can power themselves on-site from available ambient energy. Magnetic energy harvesters (MEHs), configured as current transformers, extract energy from the magnetic fields surrounding current-carrying power lines. As maximum power harvest occurs when a magnetic core is on the verge of saturation or saturated to some degree, modeling of magnetic energy harvesters is inherently difficult and nonlinear. This article proposes generalized analytical methods for modeling magnetic energy harvester behavior and validates these methods along with existing circuit model techniques. Intuition for core saturation behavior is presented and agreement with existing models is discussed. The analysis is motivated by addressing the feasibility of a split core magnetic energy harvester to power a microcontroller unit, and the models are experimentally validated for multiple harvester cores. [ABSTRACT FROM AUTHOR]

Convolutional Neural Network (CNN) inference on a resource-constrained Internet-of-Things (IoT) device (i.e., ARM Cortex-M microcontroller) requires careful optimization to reduce the timing overhead. We propose two novel techniques to improve the computational efficiency of CNNs by targeting low-cost microcontrollers. Our techniques utilize on-chip memory and minimize redundant operations, yielding low-latency inference results on complex quantized models such as MobileNetV1. On the ImageNet dataset for per-layer quantization, we reduce inference latency and Multiply-and-Accumulate (MAC) per cycle by 22.4% and 22.9%, respectively, compared to the state-of-the-art mixed-precision CMix-NN library. On the CIFAR-10 dataset for per-channel quantization, we reduce inference latency and MAC per cycle by 31.7% and 31.3%, respectively. The achieved low-latency inference results can improve the user experience and save power budget in resource-constrained IoT devices. [ABSTRACT FROM AUTHOR]

The advancements in machine learning (ML) opened a new opportunity to bring intelligence to the low-end Internet-of-Things (IoT) nodes, such as microcontrollers. Conventional ML deployment has high memory and computes footprint hindering their direct deployment on ultraresource-constrained microcontrollers. This article highlights the unique requirements of enabling onboard ML for microcontroller-class devices. Researchers use a specialized model development workflow for resource-limited applications to ensure that the compute and latency budget is within the device limits while still maintaining the desired performance. We characterize a closed-loop widely applicable workflow of ML model development for microcontroller-class devices and show that several classes of applications adopt a specific instance of it. We present both qualitative and numerical insights into different stages of model development by showcasing several use cases. Finally, we identify the open research challenges and unsolved questions demanding careful considerations moving forward. [ABSTRACT FROM AUTHOR]

Saber is a module-lattice-based key encapsulation scheme that has been selected as a finalist in the NIST Post-Quantum Cryptography standardization project. As Saber computes on considerably large matrices and vectors of polynomials, its efficient implementation on memory-constrained IoT devices is very challenging. In this paper, we present an implementation of Saber with a minor tweak to the original Saber protocol for achieving reduced memory consumption and better performance. We call this tweaked implementation ‘Saber+’, and the difference compared to Saber is that we use different generation methods of public matrix $\boldsymbol{A}$ A and secret vector $\boldsymbol{s}$ s for memory optimization. Our highly optimized software implementation of Saber+ on a memory-constrained RISC-V platform achieves 48% performance improvement compared with the best state-of-the-art memory-optimized implementation of original Saber. Specifically, we present various memory and performance optimizations for Saber+ on a memory-constrained RISC-V microcontroller, with merely 16KB of memory available. We utilize the Number Theoretic Transform (NTT) to speed up the polynomial multiplication in Saber+. For optimizing cycle counts and memory consumption during NTT, we carefully compare the efficiency of the complete and incomplete-NTTs, with platform-specific optimization. We implement 4-layers merging in the complete-NTT and 3-layers merging in the 6-layer incomplete-NTT. An improved on-the-fly generation strategy of the public matrix and secret vector in Saber+ results in low memory footprint. Furthermore, by combining different optimization strategies, various time-memory trade-offs are explored. Our software implementation for Saber+ on selected RISC-V core takes just 3,809K, 3,594K, and 3,193K clock cycles for key generation, encapsulation, and decapsulation, respectively, while consuming only 4.8KB of stack at most. [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

Recent research showcased several cyber-attacks against unmodified licensed vehicles, demonstrating the vulnerability of their internal networks. Many solutions have already been proposed by industry and academia, aiming to detect and prevent cyber-attacks targeting in-vehicle networks. The majority of these proposals borrow security algorithms and techniques from the classical ICT domain, and in many cases they do not consider the inherent limitations of legacy automotive protocols and resource-constrained microcontrollers. This paper proposes DAGA, an anomaly detection algorithm for in-vehicle networks exploiting $n-$ gram analysis. DAGA only uses sequences of CAN message IDs for the definition of the $n-$ grams used in the detection process, without requiring the content of the payload or other CAN message fields. The DAGA framework allows the creation of detection models characterized by different memory footprints, allowing their deployment on microcontrollers with different hardware constraints. Experimental results based on three prototype implementations of DAGA showcase the trade off between hardware requirements and detection performance. DAGA outperforms the state-of-the-art detectors on the most performing microcontrollers, and can execute with lower performance on simple microcontrollers that cannot support the vast majority of IDS approaches proposed in literature. As additional contributions, we publicly release the full dataset and our reference DAGA implementations. [ABSTRACT FROM AUTHOR]

The low-cost, simple, and fast quantitative assay of magnetic nanoparticles (MNPs) is important for the development of magnetic-based immunoassay applications. However, the bulky sensing element and instruments of the recent iron oxide-based MNPs assays are still concerns that should be resolved. This article reports the new platform of an iron oxide-based MNPs label assay using the commercial giant magnetoresistance (GMR) chip AAL024, manufactured by Nonvolatile Electronics (NVE) Corporation, complemented with a basic differential amplifier circuit and Arduino microcontroller (AM) to acquire the digital output voltage. The as-prepared Fe3O4@Ag label possessed (15 ± 2.6) nm of average size and behaved as soft ferromagnetic with 52.1 emu/g of saturation magnetization, and 0.15 kOe of coercive field. Sensor performance for magnetic field detection, as well as Fe3O4@Ag nanoparticles label assay, was evaluated. The results show the implementation of a basic differential amplifier op-amp circuit succeed to magnify the sensor’s response to the magnetic field up to 23 times with the output voltage in the order of volt. The employment of the AM as a voltage supply of the GMR chip, an analog-to-digital converter, and a voltage gauge simplifies the data acquisition without the additional measuring instrument. Meanwhile, for the purpose of the Fe3O4@Ag nanoparticles label assay, the sensor revealed promising performance due to the high signal linearity and the rapid detection which is only 30 s with acceptable signal stabilities. [ABSTRACT FROM AUTHOR]

Microprobing is applied to intercept data from on-chip signals, such as data passing through a data bus. Hence, it allows for extracting a full dump of this data, e.g., the firmware of a microcontroller, cryptographic key material, or any other type of passing data on the physical metal lines and/or the physical cells of the data bus connected to the metal lines. It is categorized as an invasive and physical attack vector against which software measures are insufficient for protection. As a countermeasure detecting microprobing attacks and enabling appropriate protection mechanisms, we propose a new probing detector for an industrial sub-40-nm advanced process node. It is based on ring oscillators (ROs), which are formed from the data bus lines. The oscillation frequency, caused by the capacity of bus lines, is measured and compared to detect any attached microprobes. The concept is optimized for detection of placed microprobes on both regular and irregular data buses or on any other pair of lines. For this purpose, a statistics-driven decision is made to distinguish probed from not probed lines. To improve the concept for high capacitance irregular lines, a hybrid design and test time calibration is proposed and analyzed, which shows the applicability of the concept under irregular bus lines, local variations, and jittery conditions. The results show that the approach results in low false positive (FP) and false negative (FN) rate at lower overhead comparing with alternative approaches. [ABSTRACT FROM AUTHOR]

This paper considers distributed estimation methods to enable the formation of Unmanned-Aerial-Vehicles (UAVs) that track a moving target. The UAVs (or agents) are equipped with communication devices to receive a beacon signal from the target and share information with neighboring UAVs. The shared information includes the time-of-arrival (TOA) of the beacon signal from the target and estimates on the target’s location. Every UAV processes the received information from the neighbors using a single-time-scale distributed estimation protocol. This differs from multi-time-scale protocols that require (i) many consensus iterations on a-priori estimates, (ii) fast communication among agents (in general, much faster than the sampling rate of the target dynamics), and thus, more-costly communication equipment and processing units. Further, our approach outperforms most single-time-scale methods in terms of observability assumption as these methods assume that the target is observable via the measurement data received from neighboring UAVs (referred to as local-observability). This requires more communications among the sensors. In contrast, our approach is only based on global-observability assumption, and thus, requires less networking (only strong-connectivity) and communication traffic along with less computational load by data-processing once at the same time-scale of sampling target dynamics. We consider modified time-difference-of-arrival (TDOA) measurements with a constant output matrix for the linearized model. UAVs make a pre-specified formation, and by estimating the target’s location via these measurements, move along with the target. Note to Practitioners—Inspired by recent development in industrial UAVs along with emerging progress in low-cost processing units, fog computing systems, and wireless communications, this paper considers mobile tracking of a moving target via a group of wireless-connected autonomous drones. In the classical tracking methods, which are prone to single-point-of-failure, all the sensors need to send their information to a ground central station over a long-range and costly data-transmission channel. In contrast, by collaborative tracking the processing and decision-making are distributed among a swarm of drones equipped with onboard miniaturized electronic parts such as sensors, microcontrollers, microprocessors, and communication units. This article provides an efficient algorithm to enable such drones to autonomously track the moving target in real-time. Note that the cost and tracking ability of the UAV swarm are directly determined by the computational efficiency and communication burden of the estimation algorithm. In this regard, most available estimation algorithms are over budget and even infeasible due to the need for fast data-transmission channels, fast CPUs, and high network traffic. Our proposed estimation technique outperforms similar algorithms in terms of required communication bandwidth, data-transmission rate, and computational resources, which considerably reduces the hardware cost and improves tracking efficiency in real-time large-scale applications. We show the feasibility and efficiency of our distributed tracking method by simulation. [ABSTRACT FROM AUTHOR]

Locomotion through rolling is attractive compared to other forms of locomotion thanks to uniform designs, high degree of mobility, dynamic stability, and self-recovery from collision. Despite previous efforts to design rolling soft systems, pneumatic and other soft actuators are often limited in terms of high-speed dynamics, system integration, and/or functionalities. Furthermore, mathematical description of the rolling dynamics for this type of robot and how the models can be used for speed control are often not mentioned. This article introduces a cylindrical-shaped shell-bulging rolling soft wheel that employs an array of 16 folded-HASEL actuators as a mean for improved rolling performance. The actuators represent the soft components with discrete forces that propel the wheel, whereas the wheel's frame is rigid but allows for smooth, continuous change in position and speed. We discuss the interplay between the electrical and mechanical design choices, the modeling of the wheel's hybrid (continuous and discrete) dynamic behavior, and the implementation of a model predictive controller (MPC) for the robot's speed. With the balance of several design factors, we show the wheel's ability to carry integrated hardware with a maximum rolling speed at 0.7 m/s (or 2.2 body lengths per second), despite its total weight of 979 g, allowing the wheel to outperform the existing rolling soft wheels with comparable weights and sizes. We also show that the MPC enables the wheel to accelerate and leverage its inherent braking capability to reach desired speeds—a critical function that did not exist in previous rolling soft systems. [ABSTRACT FROM AUTHOR]

The monitoring of presence is a timely topic in intelligent building management systems. Nowadays, most rooms, halls, and auditoriums use a simple binary presence detector that is used to control the operation of HVAC systems. This strategy is not optimal and leads to significant amounts of energy being wasted due to inadequate control of the system. Therefore, knowing the exact person count facilitates better adjustment to current needs and cost reduction. The vision-based people-counting is a well-known area of computer vision research. In addition, with rapid development in the artificial intelligence and IoT sectors, power-limited and resource-constrained devices like single-board computers or microcontrollers are able to run even such sophisticated algorithms as neural networks. This capability not only ensures the tiny size and power effectiveness of the device but also, by definition, preserves privacy by limiting or completely eliminating the transfer of data to the cloud. In this paper, we describe the method for efficient occupancy estimation based on low-resolution thermal images. This approach uses a U-Net-like convolutional neural network that is capable of estimating the number of people in the sensor’s field of view. Although the architecture was optimized and quantized to fit the limited microcontroller’s memory, the metrics obtained by the algorithm outperform the other state-of-the-art solutions. Additionally, the algorithm was deployed on a range of embedded devices to perform a set of benchmarks. The tests carried out on embedded processors allowed the comparison of a wide range of chips and proved that people counting can be efficiently executed on resource-limited hardware while maintaining low power consumption.

Photovoltaic (PV) devices are one of the most renewable energy sources in demand globally. To harvest the maximum possible energy output from PV panels, it is necessary to orient them in a position where the sunray can fall on them perpendicularly. In this paper, an autonomous dual-axis smart solar tracking system is designed and implemented for positioning PV panels in a way that would make them generate the highest achievable energy output automatically anywhere in the world. The designed tracking system is built based on a mathematical model which is integrated with a microcontroller ( $\mu \text{C}$ ), a Global Positioning System (GPS), a digital compass, and a gyro orientation sensor. The designed system provides a smart solution to accurately track the sun at a minimum power budget to increase the overall efficiency of PV panels. The suggested model is implemented and tested using 50 W PV panels, and it is empirically tested in the Middle East region of Baghdad, IRAQ. For further evaluation, it is also tested using simulated tracking data collected from three different regions Berlin, Singapore, and Sydney. This was done by selecting a city above the Tropic of Cancer, a city below the Tropic of Capricorn, and a city within the tropical region near the Equator. The obtained results confirmed that the developed system can track the sun in any region around the world, optimizing power consumption by operating the tracker within specific intervals that enables mustering maximum possible power of PV panels while ensuring minimum power consumption by the tracking system. The developed tracking system expended a mere 0.62% to 0.68% of the energy gain made.

This paper presents the improvement of the wave maker control system. The wave maker is a facility widely used in hydromechanics laboratories to generate waves in towing tanks. It is equipped with an electrohydraulic drive and an actuator submerged into water. The waves are generated to model the environmental conditions for physical experiments, performed on reduced-scale models of maritime objects. The physical experiments allow to predict the behaviour of full-scale objects and prove the results of numerical analyses. The overriding goal of the fluid dynamics experiments is to improve the human safety and survivability of constructions. The reported investigation and application works were vital for the improvement of physical model tests. The optimization of the proportional controllers was performed in terms of the Integral of Squared Error (ISE). The final evaluation was performed in terms of the frequency response characteristic. The results of the proportional control optimization were evaluated versus the previously applied control. The experimental research was conducted in the real towing tank located at the Maritime Advanced Research Centre. The investigation has shown the advantage of the ISE optimized conventional proportional control. It has particularly proven the affordability and swiftness of the optimization process. It also proved a more efficient frequency response of the wave maker obtained within a required and reasonable lead time. The performed investigation has greatly contributed to the development of a new method of physical experiments in white noise waves. The results related to this new more efficient method are presented as well.

Table-based scalar multiplication provides practical security for ECDSA signature generation. However, a novel key recovery attack against this form of ECDSA signature generation that exploits the collisions between entries was recently proposed at CHES 2021. This attack is possible even if table entries are unknown, such as with random permutated entry ordering. In this paper, we enhance the efficiency of the key recovery attack against secure ECDSA signature generation based on fixed-base comb scalar multiplication. We significantly reduce the required number of traces by compressing collision information using the mathematical relationship between table entry collisions. We verify this is a practical threat by performing an experiment on fixed-base comb method with window width $w=4$ w = 4 . Using our method, up to 27 traces are needed, much fewer than 1,019 traces required in the CHES publication. We cluster real traces measured using 32-bit STM32F4 microcontroller. In the experiment, we provide a selection method of points of interest using variance traces and unsupervised clustering-based leakage detection. With the selection method, we succeed in clustering leakages into 16 classes with a 100% success rate with 32-bit MCU. This represents the first experiment to cluster the more leakage classes with a 32-bit MCU than in literature. [ABSTRACT FROM AUTHOR]

Machine learning model deployment for training and execution has been an important topic for industry and academic research in the last decade. Much of the attention has been focused on developing specific toolchains to support acceleration hardware. In this article, we present Intermediate Representation Execution Environment (IREE), a unified compiler and runtime stack with the explicit goal to scale down machine learning programs to the smallest footprints for mobile and edge devices, while maintaining the ability to scale up to larger deployment targets. IREE adopts a compiler-based approach and optimizes for heterogeneous hardware accelerators through the use of the Multi-Level IR (MLIR) compiler infrastructure, which provides the means to quickly design and implement multilevel compiler intermediate representations (IR). More specifically, this article is focused on TinyIREE, which is a set of deployment options in IREE that accommodate the limited memory and computation resources in embedded systems and bare-metal platforms, while also demonstrating IREE's intuitive workflow that generates workloads for different ISA extensions and application binary interface (ABIs) through LLVM. [ABSTRACT FROM AUTHOR]

This brief introduces a novel bioinspired motor neuron dynamical unit where the neural dynamics, responsible for the generation of the action potentials, is embedded into the actuator dynamics, which here plays the role of, and substitutes, the recovery variable into the classical neuron equations. A recently introduced nullcline-based control strategy, over servomotors embedded into piecewise linearly approximated FitzHugh–Nagumo neuron models, is here applied to the synchronization of two embodied motor-neuron units in the form of either a continuously active proportional gain or an event-driven strategy. In view of the application to such problems as the generation of adaptive control laws for distributed oscillatory networks, at the basis of bioinspired walking machines, the advantages in terms of the reduced-order dynamical equations and ease of synchronization are presented both through simulations and with experiments devoted to control networked Dynamixel MX-28AT servomotors via an microcontroller unit (MCU) board. [ABSTRACT FROM AUTHOR]

Recent proliferation of CPS and IoT devices has led to an increasing demand for analyzing performance and timing of event-driven computational activity, especially interrupts and exceptions. However, these devices typically lack hardware resources, power, and system-software infrastructure for profiling/monitoring such events. Even when feasible, the profiling/monitoring activity itself can perturb the performance and timing of the timing-sensitive activity to be analyzed, therefore producing misleading results. Thus, we present Primer, a novel approach for profiling interrupts. Primer leverages existing unintentional (side-channel) electromagnetic emanations of the profiled/monitored device to identify its asynchronous execution (e.g., interrupt handlers). Primer leaves the monitored system (and its behavior) completely unchanged, requires no system resources or support, and introduces neither overheads nor perturbation in the monitored system. We validate Primer by analyzing signals that correspond to five different types of interrupts on an IoT device (ARM Cortex-M), achieving 99.5% accuracy (with no false positives), and on an MSP430 microcontroller-based device with even better accuracy. We also demonstrate the effectiveness of Primer in analyzing page faults and network interrupts when executing real-world applications on a more sophisticated embedded device (ARM Cortex-A8), and show that the results provided by Primer can provide useful insights about an application's interaction with the system's virtual memory and network-oriented services. [ABSTRACT FROM AUTHOR]

The coupling of short wavelength electromagnetic (EM) interference to critical electronic systems in highly reverberant enclosures is a growing concern in the EM interference/compatibility community. In such highly reverberant cavities, prior research has shown that the induced EM fields, voltages, or currents can be modeled using the wave-chaotic random coupling model (RCM). The RCM partitions the interaction within the cavity into a universally fluctuating part, derived from random matrix theory, and a system-specific part, defined by the radiation impedance of the ports of interest, where the voltages or currents are induced. Earlier researchers have treated the radiation impedance as a time-invariant, frequency-dependent complex quantity. This is true for passive structures but is not true for active semiconductor devices, such as microcontrollers, which can exhibit time-varying radiation properties depending on the instruction cycle being executed at a given instant of time. The estimate of such a time-varying radiation impedance and its correlation with instruction cycles in an elemental microcontroller is the focus of this work. Utilizing clustering algorithms, we observe that the measured radiation impedance, as well as radiative emissions, are correlated to the class of instruction cycles being executed. By clustering the radiation impedance and emissions of the general-purpose input/output ports utilizing the class of instructions being executed, predictive models for microcontroller susceptibility can be derived even when detailed knowledge of the specific instruction cycle being executed is unknown a priori. Such a predictive capability can find multiple applications in the EMI/EMC community. [ABSTRACT FROM AUTHOR]

In this article, a novel method is proposed for determining the running state of a system through the classification of electromagnetic interference (EMI) leakage using neural network (NN) models. A modified IEC 61967 measurement platform is used to analyze the EMI signals of a microcontroller unit during its operation. A total of 17 NN models are developed and tested to determine the optimal model. The optimal NN model has ungrouped-Top3 and ungrouped-Top5 accuracies of 77.13% and 91.94%, respectively. The ungrouped-Top1 accuracy is improved by 7.53%. They are the highest improvements ever achieved to the best of the author's knowledge. [ABSTRACT FROM AUTHOR]

This article introduces an original microcontroller unit (MCU) design of numerical low-pass (LP) negative group delay (NGD) function. The innovative theory of the numerical LP-NGD function is developed based on the first-order analog transfer function discretization. The infinite impulse response (IIR) LP-NGD is fundamentally formulated in function of the desired NGD value, cutoff frequency, gain, and the MCU sampling frequency. A STM32 MCU proof-of-concept (POC) is tested to implement the IIR LP-NGD function. Different real-time tests with visualization of input and output analog signals from the MCU LP-NGD POC were performed. As expected, time-advance demonstration tests with milli-second short- and several hour long-duration time-scale with arbitrary waveform signals from temperature and humidity sensors. The signal time-advance is not in contradiction with the causality. The proposed digital MCU function opens a potential future industrial application of LP-NGD function via sensored signal anticipation. [ABSTRACT FROM AUTHOR]

In vehicular edge computing networks, electric vehicles can get charging services from edge servers through some road-side charging stations. Several recent studies have investigated how to deal with security requirements in these communications. Nevertheless, simultaneous provision of security and lightness, which is crucial for resource-constrained vehicles, is still an open issue. More critically, the anonymity from the perspective of honest-but-curious edge nodes has not been yet addressed. Thus, this paper proposes a novel ultra-lightweight framework for the secure and anonymous communications of vehicles during their charging reception by means of blockchain. Thanks to the blockchain technology, the accountability of electric vehicle possessors guaranteed. The proposed scheme has been validated in terms of security metrics and also implemented on two ARM-based platforms, one 32-bit ARM microcontroller and one 64-bit ARM processor. Further, its blockchain part has been deployed on a Hyperledger Fabric network. The obtained results besides the comparison with well-respected similar schemes acknowledge the usefulness and practicability of the presented scheme. [ABSTRACT FROM AUTHOR]

Contribution: This article presents an innovative course sequence to integrate Electrical Engineering (EE) Fundamentals into the Mechanical Engineering (ME) Instrumentation and Data Acquisition (DAQ) course and reports students’ experience relevant to the sequence’s intended outcomes of helping students learn and connect EE concepts with ME applications and develop their engineering identities. Background: The ME Department at Seattle University was awarded a National Science Foundation Grant to revolutionize its undergraduate program. This project focuses on doing engineering to foster stronger engineering identities. This course sequence is part of the curriculum change for this project and includes open-ended, real-world labs incorporating both EE and DAQ. Research Questions: 1) Engineering Learning: What evidence is there that students learned EE and DAQ concepts and integrated them with ME? 2) Identity Development: How did the students connect the experience to their evolving identity as engineers? 3) Over-Time Experience: How did students experience the course? Methodology: A mix of quantitative and qualitative data was used: quantitative data (a standardized test) and qualitative data source (mini reflections that students provided over the course sequence) were analyzed to address the research questions that connect the educational design aspects and the intended outcomes. Findings: The new course sequence created an opportunity to do engineering in a rich way and provided fertile ground for developing engineering identities. Students understood and retained EE and DAQ concepts at a level equal to when the material was taught via separate courses. [ABSTRACT FROM AUTHOR]

This article presents an L2 norm-enabled variable step-size adaptive least mean square controller for grid-connected photovoltaic converter. The variable step size is adopted to damp out the weight oscillations and to enable faster convergence under exposure to disturbances in the load and solar insolation. More precisely, to achieve oscillations free response, a nonlinear relationship is developed between step size and estimated error. This way, it significantly improves the convergence speed and stability. The iteration function of the presented variable step-size feature includes the input signal to study the impact of harmonically polluted load current on the weight extraction performance. Besides, the designing procedure of step size considers both current and previous error states, thereby ensuring noise immunity. With the inclusion of these features, the devised controller is applied to accurately extracting the fundamental weight component of the load current and in turn enabling various ancillary services. The proposed control algorithm is designed in matlab/Simulink software and its effectiveness is examined under both steady-state and transient conditions during grid disturbances. Furthermore, the practicability of the proposed controller is verified and compared with conventional controls using ARM cortex M4 microcontroller-based laboratory test bed. In a nutshell, the results confirm the oscillations free weight component with higher convergence and better stability under various operating conditions. [ABSTRACT FROM AUTHOR]

Digitally printed conductive structures often need to be electrically connected to batteries, microcontrollers, or other devices. A consensus of industry and research is that such hybrid printed electronics will play a major part in the future of printed electronics. To promote the technology of hybrid printed electronics, surface mount technologies for electronic components using isotropic conductive adhesives (ICAs) and low melting tin bismuth solders on inkjet-printed silver structures on injection molded liquid crystal polymer (LCP) substrates were investigated in this publication. The special needs for inkjet-printed electronics were considered as well as the reliability of assembled surface mounted devices (SMDs) and their failure mechanisms. Connected 0603 and 1206 SMD components achieved a characteristic fatigue life of more than 3500 cycles during thermal cycling at +125 °C/−40 °C and withstood over 1000 h under a damp-heat atmosphere of +85 °C/85% RH. The coefficient of thermal expansion (CTE) of the substrate and the selection of solder have major impacts on the reliability of the assemblies. [ABSTRACT FROM AUTHOR]

The label "Harvard architecture" has been applied to various computing devices where instructions and data are stored in separate memories. In the Harvard Mark III/IV the decision to separate the stores was motivated by a desire to optimize each form of storage, not by Aiken's oft-quoted antagonism toward "self-modifying code," which was anyway not justified even at the time, and would become a liability with the emergence of operating systems. The term "Harvard architecture" was coined decades later, in the context of microcontroller design, retrospectively applied to the Harvard machines, and subsequently applied to RISC microprocessors with separated caches. The so-called "Harvard" and "von Neumann" architectures are often portrayed as a dichotomy, but the various devices labeled as the former have far more in common with the latter than they do with each other. [ABSTRACT FROM AUTHOR]

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes. [ABSTRACT FROM AUTHOR]

In distributed real-time communication systems, common knowledge of the global time is crucial. It prevents message violations on the bus and allows independent components to collaborate within a real-time system on a timely basis. Systems with hard real-time requirements need to have high precision and accuracy of time. This is achieved by hardware-supported frame time-stamping mechanisms as found in dedicated protocols, such as time-triggered CAN (TTCAN), Flexray, and time-sensitive networking (TSN)-enabled Ethernet. However, many microcontroller units are not specifically designed to provide such a hardware-based solution at the communication interface. Therefore, a software-based implementation of the time synchronization algorithm is needed. Nevertheless, some commercial off-the-shelf (COTS) microcontroller units already provide an IEEE 1588-enabled Ethernet interface, including a high-precision timer module with rate correction. This module can be used for time synchronization purposes to align a set of distributed clocks via various communication interfaces. This article investigates the accuracy of software-based and hardware-supported time synchronization algorithm over the controller area network (CAN) protocol using a COTS microcontroller. As a result, we present identified jitter and delay sources as well as the achieved time accuracy. We show that using an advanced timer module combined with additional system knowledge allows submicrosecond precision and accuracies. [ABSTRACT FROM AUTHOR]

This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- $\mu \text{W}$ power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8. [ABSTRACT FROM AUTHOR]

In this paper, a reliable methodology is proposed in order to implement and validate a Model Predictive Control (MPC) scheme on an actual Voltage Source Converter (VSC) integrated in a scale-down multi-terminal DC grid. The objective of the investigated MPC controller is to enable AC frequency support among two asynchronous AC areas through a High Voltage Direct Current (HVDC) grid, while considering physical constraints, such as maximum and minimum DC voltage. A systematic and accurate implementation strategy is proposed, based mainly on the Hardware In the Loop (HIL) and Power Hardware In the Loop (PHIL), leading to the real-life testing on VSC, controlled by a classical microcontroller. The technical problems during the implementation process, as well as the proposed solutions, are described in detail through this paper. This procedure is deemed valuable to bridge the gap between offline simulation and the actual implementation of such advanced control scheme on experimental test rig. [ABSTRACT FROM AUTHOR]

A sample-data modeling strategy for a 30-kW, two-phase dual interleaved buck–boost converter with peak current control is analyzed in this article. A small-signal converter model is derived to characterize the system utilizing the current peaks of the two interleaved phases and a half-symmetry, state-space representation of the circuit. The model is experimentally verified using a 32-kW, 350-V prototype that owns 7.6 kW/kg and 97.1% of power density and efficiency, respectively. A description of the controller, developed in a high-performance microcontroller, is also presented together with the experimental verification, detailing the design of the compensating ramp for a wide load range. Measured results are contrasted with the sample-data model predictions, using both transient and frequency responses, and evaluating the controlled converter dynamics at 14, 21, 26, and 30 kW. The comparison reveals the effective validity of the presented sample-data model and the effects of the supply to the dynamic performance of the high-density converter. [ABSTRACT FROM AUTHOR]

Flexural ultrasonic transducers experience sustained residual vibrations after their excitation has ended. This behavior limits both the minimum range and the range resolution of single-transducer distance sensors operating in pulse-echo mode. Two methods are presented to address residual vibration issues without reducing the intensity of the transmitted pressure waves. The first method is a transmitter enhancement; a number of out-of-phase damping cycles is appended to the desired number of excitation cycles, thereby hastening the decay of the pulse-imposed transducer voltage. The second method is a receiver enhancement; the echo-induced transducer voltage is isolated from the pulse-imposed transducer voltage by subtracting a stored masking signal from the acquired receiver signal. The proposed methods rely on a simple learning procedure that does not require a mathematical model of the system. Because this procedure is executed on an embedded microcontroller, the proposed methods are insensitive to variations in components or parameters. Experiments demonstrate improvements in both minimum range and range resolution. [ABSTRACT FROM AUTHOR]

Many embedded systems operate under real-time conditions. For them, the worst case execution time (WCET) is a crucial information to check whether the software implementation meets the requirements. In modern microcontrollers, this WCET can often no longer be evaluated statically since these processors include too many unpredictable components (cache, bus arbitration, $\ldots$ ,). Here, hybrid WCET estimation comes into play, where measured traces are used to empirically compute bounds for the WCET. For meaningful estimations, it is required to put each measured segment into a corresponding execution context. In this contribution, we present a method that allows to gather such context-sensitive statistics online in hardware. This enables arbitrary long measurement intervals with a precision that compares to state-of-the-art offline tools. [ABSTRACT FROM AUTHOR]

We present a hybrid analog/digital computing circuit to solve a selective harmonic minimization problem. The approach leverages favorable attributes of digital and analog controllers to yield a fast and scalable optimization solver. A digital microcontroller programs the cost function and other user-defined inputs to the optimization problem. Voltages in the circuit represent switching angles. In steady state, the voltages converge to Karush–Kuhn–Tucker (KKT) points of the problem. We present a specific realization of the computing circuit that solves for eight independent switching angles for a quarter-wave symmetric pulsewidth modulation (PWM) driven two-level single-phase inverter. Seven undesired harmonics are minimized while retaining control over the modulation index. The proposed computing circuit is verified with simulations and a hardware implementation. The experimental results demonstrate that the proposed circuit can converge to the optimal solution in less than 5.0 ms, which is substantially faster than the existing methods and facilitates real-time implementation. Moreover, the steady-state power consumption of the hardware implementation is approximately 750 mW, which is also significantly lower than the published methods for comparable applications. The computing circuit is utilized to generate the PWM for a 2-kW single-phase inverter, which validates its feasibility in practical applications. [ABSTRACT FROM AUTHOR]

In the field of agriculture, growth monitoring and measurement are two important factors used specifically to evaluate the influence of the environmental conditions on productivity. The change of circumference of parts of plants like their trunks, branches and fruits is one way to monitor plant growth. In this paper, we developed an Internet of Things (IoT)-based growth measurement and monitoring system using a 2-Axis joystick. In the case study, we measured the growth of Jackfruit which is a tropical fruit and widely cultivated in tropical areas like India, Bangladesh, Thailand, Brazil, and Malaysia. The developed appliance is referred to as AgriStick. The IoT appliance utilizes a 16-bit ultra-low power consuming microcontroller. We used RS485 protocol to make our appliance work for long distance range. The sensor was utilized for the purpose of monitoring the growth of horticulture crops as well as natural ecosystem plants. [ABSTRACT FROM AUTHOR]

In high-speed digital systems containing dense digital devices, such as microcontrollers, microprocessors, graphic processors, network processors, switching hubs, field-programmable gate arrays, and application-specific integrated circuits (ICs), the interconnects are no longer transparent. This has been the case for systems since clock frequencies rose above 50 MHz, which includes just about all digital products used today. Unless special care is taken in their design and implementation, a high-speed system will fail due to one or more problems generally grouped into the families of signal integrity (SI), power integrity (PI), or electromagnetic interference (EMI). [ABSTRACT FROM AUTHOR]

With the outbreak of the Covid-19 pandemic, vaccination has become mandatory. Further, for effective results, the vaccines should be stored within the recommended temperature range, typically between 2°C to 8°C, transported safely without any mishandling and temperature excursion. In order to assure vaccine potency, it is essential to have detailed information on the entire temperature data recorded at user-defined intervals. In this paper, we develop functionality interaction to bring different sensors, memory, and processing units to an integrated platform, providing a compact, power-efficient, and low-cost commercial TemperatuRE, Humidity, and MOvement Data-logger (THERMOD). Moreover, the THERMOD hardware is packed with interactive algorithms that address the aforementioned concerns and log the real-time temperature and jerks (3-dimensional movement) encountered throughout the journey, and the logged data can be retrieved by plugging THERMOD into the host computer/laptop. The THERMOD hardware formulation and algorithm embedding have been done in the institution lab, which enables end-to-end storage and monitoring. Also, the proposed design is built with the defined standards by health organizations, e.g., WHO. Further, to validate the proficiency of the proposed design, comparative analysis has been done; a) a cost analysis has been done to state the cost efficiency of the proposed solution, b) real-time power performance graphs have been plotted which depict that THERMOD outperforms the existing solutions. Moreover, a number of experiments were performed for the validation of the proposed design. [ABSTRACT FROM AUTHOR]

Depth estimation is crucial in several computer vision applications, and a recent trend in this field aims at inferring such a cue from a single camera. Unfortunately, despite the compelling results achieved, state-of-the-art monocular depth estimation methods are computationally demanding, thus precluding their practical deployment in several application contexts characterized by low-power constraints. Therefore, in this paper, we propose a lightweight Convolutional Neural Network based on a shallow pyramidal architecture, referred to as $\mu $ PyD-Net, enabling monocular depth estimation on microcontrollers. The network is trained in a peculiar self-supervised manner leveraging proxy labels obtained through a traditional stereo algorithm. Moreover, we propose optimization strategies aimed at performing computations with quantized 8-bit data and map the high-level description of the network to low-level layers optimized for the target microcontroller architecture. Exhaustive experimental results on standard datasets and an in-depth evaluation with a device belonging to the popular Arm Cortex-M family confirm that obtaining sufficiently accurate monocular depth estimation on microcontrollers is feasible. To the best of our knowledge, our proposal is the first one enabling such remarkable achievement, paving the way for the deployment of monocular depth cues onto the tiny end-nodes of distributed sensor networks. [ABSTRACT FROM AUTHOR]